Texas TMS320C645X Manuale Utente
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5.50
Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP)
SRIO Registers
There are sixteen of these registers.
Figure 106. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP)
31-16
TX_CP
RW-0x00
LEGEND: R = Read only; -n = value after reset
15-0
TX_CP
RW-0x00
LEGEND: R = Read only; -n = value after reset
Table 80. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field
Descriptions
Bit
Field
Value
Description
31-0
TX_CP
This field is the host memory address for the transmit queue completion pointer. This register is
written by the host with the buffer descriptor address for the last buffer processed by the host
during interrupt processing. The port uses the value written to determine if the interrupt should be
deasserted.
written by the host with the buffer descriptor address for the last buffer processed by the host
during interrupt processing. The port uses the value written to determine if the interrupt should be
deasserted.
SPRU976 – March 2006
Serial RapidIO (SRIO)
151