Texas TMS320C645X Manuale Utente
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5.51
Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP)
SRIO Registers
There are sixteen of these registers.
Figure 107. Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP)
31-16
RX_HDP
RW-0x00
LEGEND: R = Read only; -n = value after reset
15-0
RX_HDP
RW-0x00
LEGEND: R = Read only; -n = value after reset
Table 81. Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) Field
Descriptions
Bit
Field
Value
Description
31-0
RX_HDP
Rx Queue Head Descriptor Pointer: This field is the host memory address for the first buffer
descriptor in the channel receive queue. This field is written by the host to initiate queue receive
operations and is zeroed by the port when all free buffers have been used. An error condition
results if the host writes this field when the current field value is nonzero. The address must be
32-bit word aligned.
descriptor in the channel receive queue. This field is written by the host to initiate queue receive
operations and is zeroed by the port when all free buffers have been used. An error condition
results if the host writes this field when the current field value is nonzero. The address must be
32-bit word aligned.
Serial RapidIO (SRIO)
152
SPRU976 – March 2006