Texas TMS320C645X Manuale Utente
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5.52
Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP)
SRIO Registers
There are sixteen of these registers.
Figure 108. Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP)
31-16
RX_CP
RW-0x00
LEGEND: R = Read only; -n = value after reset
15-0
RX_CP
RW-0x00
LEGEND: R = Read only; -n = value after reset
Table 82. Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP) Field
Descriptions
Bit
Field
Value
Description
31-0
RX_CP
Rx Queue Completion Pointer: This field is the host memory address for the receive queue
completion pointer. This register is written by the host with the buffer descriptor address for the last
buffer processed by the host during interrupt processing. The port uses the value written to
determine if the interrupt should be deasserted.
completion pointer. This register is written by the host with the buffer descriptor address for the last
buffer processed by the host during interrupt processing. The port uses the value written to
determine if the interrupt should be deasserted.
SPRU976 – March 2006
Serial RapidIO (SRIO)
153