Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2 Manuale Utente
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HYS64T128000EU-2.5C2
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.0, 2008-06
18
06112008-YHWK-B105
3.4
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol
DDR2–800 DDR2–667 Unit
Note
Min.
Max.
Min.
Max.
CAS to CAS command delay
t
CCD
2
—
2
—
nCK
Average clock high pulse width
t
CH.AVG
0.48
0.52
0.48
0.52
t
CK.AVG
Average clock period
t
CK.AVG
2500
8000
3000
8000
ps
CKE minimum pulse width ( high and
low pulse width)
low pulse width)
t
CKE
3
—
3
—
nCK
Average clock low pulse width
t
CL.AVG
0.48
0.52
0.48
0.52
t
CK.AVG
Auto-Precharge write recovery +
precharge time
precharge time
t
DAL
WR +
t
nRP
—
WR +
t
nRP
—
nCK
Minimum time clocks remain ON after
CKE asynchronously drops LOW
CKE asynchronously drops LOW
t
DELAY
t
IS
+
t
CK .AVG
+
t
IH
––
t
IS
+
t
CK .AVG
+
t
IH
––
ns
DQ and DM input hold time
t
DH.BASE
125
––
175
––
ps
DQ and DM input pulse width for each
input
input
t
DIPW
0.35
—
0.35
—
t
CK.AVG
DQS input high pulse width
t
DQSH
0.35
—
0.35
—
t
CK.AVG
DQS input low pulse width
t
DQSL
0.35
—
0.35
—
t
CK.AVG
DQS-DQ skew for DQS & associated
DQ signals
DQ signals
t
DQSQ
—
200
—
240
ps
DQS latching rising transition to
associated clock edges
associated clock edges
t
DQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
t
CK.AVG
DQ and DM input setup time
t
DS.BASE
50
––
100
––
ps
DQS falling edge hold time from CK
t
DSH
0.2
—
0.2
—
t
CK.AVG
DQS falling edge to CK setup time
t
DSS
0.2
—
0.2
—
t
CK.AVG
Four Activate Window for 1KB page
size products
size products
t
FAW
35
—
37.5
—
ns
Four Activate Window for 2KB page
size products
size products
t
FAW
45
—
50
—
ns
CK half pulse width
t
HP
Min(
t
CH.ABS
,
t
CL.ABS
)
__
Min(
t
CH.ABS
,
t
CL.ABS
)
__
ps
Data-out high-impedance time from
CK / CK
CK / CK
t
HZ
—
t
AC.MAX
—
t
AC.MAX
ps
Address and control input hold time
t
IH.BASE
250
—
275
—
ps
Control & address input pulse width
for each input
for each input
t
IPW
0.6
—
0.6
—
t
CK.AVG
Address and control input setup time
t
IS.BASE
175
—
200
—
ps
DQ low impedance time from CK/CK
t
LZ.DQ
2 x
t
AC.MIN
t
AC.MAX
2 x
t
AC.MIN
t
AC.MAX
ps