Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2 Manuale Utente

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HYS64T128000EU-2.5C2

HYS[64/72]T512020EU–[25F/2.5/3S]–A

Unbuffered DDR2 SDRAM Modules

Internet Data Sheet

Rev. 1.0, 2008-06

06112008-YHWK-B105

DDR2–533, ‘

‘ is used for both concepts. Example:

= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command

may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x

CK.AVG

ERR.2PER(Min)

8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual

ERR(6-10per)

of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has

ERR(6-10PER).MIN

= – 272

ps and

ERR(6- 10PER).MAX

= + 293 ps, then

DQSCK.MIN(DERATED)

DQSCK.MIN

–

ERR(6-10PER).MAX

= – 400 ps – 293 ps = – 693 ps and

DQSCK.MAX(DERATED)

DQSCK.MAX

–

ERR(6-10PER).MIN

= 400 ps + 272 ps = + 672 ps. Similarly,

LZ.DQ

for DDR2–667 derates to

LZ.DQ.MIN(DERATED)

= - 900 ps – 293 ps = – 1193 ps and

LZ.DQ.MAX(DERATED)

= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)

9) Input clock jitter spec parameter. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values.
11)

CKE.MIN

of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of

+ 2 x

12) DAL = WR + RU{

(ns) /

(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For

, if the result

of the division is not already an integer, round up to the next highest integer.

refers to the application clock period. Example: For

DDR2–533 at

= 3.75 ns with

programmed to 4 clocks.

DAL

= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

13)

DAL.nCK

= WR [nCK] +

nRP.nCK

= WR + RU{

[ps] /

CK.AVG

[ps] }, where WR is the value programmed in the EMR.

14) Input waveform timing

with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to

the input signal crossing at the

IH.DC

level for a falling signal and from the differential data strobe crosspoint to the input signal crossing

at the

IL.DC

level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between

IL.DC.MAX

and

IH.DC.MIN

. See

Figure 4

15)

DQSQ

: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output

slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e.

JIT.PER

JIT.CC

, etc.), as these are relative to the clock signal

crossing. That is, these parameters should be met whether clock jitter is present or not.

17) Input waveform timing

with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the

IH.AC

level

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the

IL.AC

level to the differential data strobe

crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between

il(DC)MAX

and

ih(DC)MIN

. See

Figure 4

18) If

is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.

19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal

((L/U/R)DQS / DQS) crossing.

20)

is the minimum of the absolute half period of the actual input clock.

is an input parameter but not an input specification parameter.

It is used in conjunction with t

QHS

to derive the DRAM output timing

. The value to be used for

calculation is determined by the

following equation;

= MIN (

CH.ABS

CL.ABS

), where,

CH.ABS

is the minimum of the actual instantaneous clock high time;

CL.ABS

is the

minimum of the actual instantaneous clock low time.

21)

and

transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level

which specifies when the device output is no longer driving (

), or begins driving (

) .

22) input waveform timing is referenced from the input signal crossing at the

IL.DC

level for a rising signal and

IH.DC

for a falling signal applied

to the device under test. See

Figure 5

23) Input waveform timing is referenced from the input signal crossing at the

IH.AC

level for a rising signal and

IL.AC

for a falling signal applied

to the device under test. See

Figure 5

24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to

its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

JIT.PER

JIT.CC

etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.

25)

–

QHS

, where:

is the minimum of the absolute half period of the actual input clock; and

QHS

is the specification value under

the max column. {The less half-pulse width distortion present, the larger the

value is; and the larger the valid data eye will be.}

Examples: 1) If the system provides

of 1315 ps into a DDR2–667 SDRAM, the DRAM provides

of 975 ps minimum. 2) If the system

provides

of 1420 ps into a DDR2–667 SDRAM, the DRAM provides

of 1080 ps minimum.

26)

QHS

accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual

at the input is

transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.

27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85

°C

and 95

°C.

28) 0 °C

≤

CASE

≤ 85 °C.

29) 85

°C <

CASE

≤ 95 °C.