Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2 Manuale Utente

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HYS64T128000EU-2.5C2
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HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
 Internet Data Sheet
Rev. 1.0, 2008-06
19
06112008-YHWK-B105
1)
V
DDQ
 = 1.8 V ± 0.1V; 
V
DD
 = 1.8 V ± 0.1 V. 
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down 
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew 
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS /  RDQS, 
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until 
V
REF
 stabilizes. During the period before 
V
REF
 stabilizes, CKE = 0.2 x 
V
DDQ
 is recognized as low.
6) The output timing reference voltage level is 
V
TT
7) New units, ‘
t
CK.AVG
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
t
CK.AVG
‘ represents the actual 
t
CK.AVG
 of the input clock 
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and 
DQS/DQS low-impedance time from 
CK / CK
t
LZ.DQS
t
AC.MIN
t
AC.MAX
t
AC.MIN
t
AC.MAX
ps
MRS command to ODT update delay
t
MOD
0
12
0
12
ns
Mode register set command cycle 
time
t
MRD
2
2
nCK
OCD drive mode output delay
t
OIT
0
12
0
12
ns
DQ/DQS output hold time from DQS
t
QH
t
HP
t
QHS
t
HP
t
QHS
ps
DQ hold skew factor
t
QHS
300
340
ps
Average periodic refresh Interval
t
REFI
7.8
7.8
μs
3.9
3.9
μs
Auto-Refresh to Active/Auto-Refresh 
command period
t
RFC
127.5
127.5
ns
Read preamble
t
RPRE
0.9
1.1
0.9
1.1
t
CK.AVG
Read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK.AVG
Active to active command period for 
1KB page size products
t
RRD
7.5
7.5
ns
Internal Read to Precharge command 
delay
t
RTP
7.5
7.5
ns
Write preamble
t
WPRE
0.35
0.35
t
CK.AVG
Write postamble
t
WPST
0.4
0.6
0.4
0.6
t
CK.AVG
Write recovery time 
t
WR
15
15
ns
Internal write to read command delay
t
WTR
7.5
7.5
ns
Exit power down to read command
t
XARD
2
2
nCK
Exit active power-down mode to read 
command (slow exit, lower power)
t
XARDS
8 – AL
7 – AL
nCK
Exit precharge power-down to any 
valid command (other than NOP or 
Deselect) 
t
XP
2
2
nCK
Exit self-refresh to a non-read 
command
t
XSNR
t
RFC
+10
t
RFC
+10
ns
Exit self-refresh to read command
t
XSRD
200
200
nCK
Write command to DQS associated 
clock edges
WL
RL – 1
RL–1
nCK
Parameter
Symbol
DDR2–800 DDR2–667 Unit
Note
1)2)3
)4)5)6)7)
 Min.
Max.
 Min.
Max.