Scheda Tecnica (AT91SAM9N12-EK)SommarioContents3List of Tables7List of Figures11Preface15About this manual16Product revision status16Intended audience16Using this manual16Conventions18Further reading20Feedback21Feedback on the product21Feedback on this manual21Introduction231.1 About the ARM926EJ-S processor24Programmer’s Model292.1 About the programmer’s model302.2 Summary of ARM926EJ-S system control coprocessor (CP15) registers312.2.1 Addresses in an ARM926EJ-S system322.2.2 Accessing CP15 registers322.3 Register descriptions352.3.1 ID Code, Cache Type, and TCM Status Registers, c0352.3.2 Control Register c1402.3.3 Translation Table Base Register c2452.3.4 Domain Access Control Register c3452.3.5 Register c4462.3.6 Fault Status Registers c5462.3.7 Fault Address Register c6482.3.8 Cache Operations Register c7482.3.9 TLB Operations Register c8522.3.10 Cache Lockdown and TCM Region Registers c9542.3.11 TLB Lockdown Register c10602.3.12 Register c11 and c12612.3.13 Process ID Register c13612.3.14 Register c14632.3.15 Test and Debug Register c1564Memory Management Unit653.1 About the MMU663.1.1 Access permissions and domains673.1.2 Translated entries673.1.3 MMU program accessible registers683.2 Address translation693.2.1 Translation table base703.2.2 First-level fetch723.2.3 First-level descriptor723.2.4 Section descriptor743.2.5 Coarse page table descriptor753.2.6 Fine page table descriptor763.2.7 Translating section references773.2.8 Second-level descriptor783.2.9 Translating large page references803.2.10 Translating small page references823.2.11 Translating tiny page references833.3 MMU faults and CPU aborts853.3.1 Fault address and fault status registers853.4 Domain access control883.5 Fault checking sequence903.5.1 Alignment faults913.5.2 Translation faults913.5.3 Domain faults913.5.4 Permission faults923.6 External aborts933.6.1 Enabling the MMU933.6.2 Disabling the MMU943.7 TLB structure95Caches and Write Buffer974.1 About the caches and write buffer984.2 Write buffer1004.3 Enabling the caches1014.4 TCM and cache access priorities1044.5 Cache MVA and Set/Way formats105Tightly-Coupled Memory Interface1095.1 About the tightly-coupled memory interface1105.2 TCM interface signals1125.2.1 Data interface signals1125.2.2 Instruction TCM signals1155.2.3 Differences between DTCM and ITCM1155.3 TCM interface bus cycle types and timing1165.3.1 Zero wait state timing1175.3.2 DMA access to zero wait state TCM1185.3.3 Multi-cycle access timing1215.4 TCM programmer’s model1275.4.1 Enabling the ITCM1275.4.2 Enabling the DTCM1275.4.3 Disabling the ITCM1275.4.4 Disabling the DTCM1275.4.5 Cachable and bufferable attributes1275.5 TCM interface examples1285.5.1 Zero-wait-state RAM example1285.5.2 Producing byte writable memory using word writable RAM1285.5.3 Multiple banks of RAM example1295.5.4 Sequential ROM example1325.5.5 DMA interface example1345.5.6 Integrating RAM test logic1355.6 TCM access penalties1375.7 TCM write buffer1385.8 Using synchronous SRAM as TCM memory1395.9 TCM clock gating140Bus Interface Unit1416.1 About the bus interface unit1426.2 Supported AHB transfers1436.2.1 Memory map1436.2.2 Transfer size1436.2.3 Mapping of level one and level two (AHB) attributes1456.2.4 Byte and halfword accesses1466.2.5 AHB system considerations1466.2.6 AHB clocking1506.2.7 External Abort limitations150Noncachable Instruction Fetches1537.1 About noncachable instruction fetches1547.1.1 Uses of noncachable code1547.1.2 Self modifying code1547.1.3 AHB behavior155Coprocessor Interface1578.1 About the ARM926EJ-S external coprocessor interface1588.1.1 Overview1588.2 LDC/STC1608.3 MCR/MRC1628.3.1 Interlocked MCR1638.4 CDP1648.5 Privileged instructions1658.6 Busy-waiting and interrupts1668.7 CPBURST1678.8 CPABORT1688.9 nCPINSTRVALID1698.10 Connecting multiple external coprocessors170Instruction Memory Barrier1719.1 About the instruction memory barrier operation1729.2 IMB operation1739.2.1 Clean the DCache1739.2.2 Drain the write buffer1739.2.3 Synchronize data and instruction streams in level two AHB subsystems1739.2.4 Invalidate the ICache1749.2.5 Flush the prefetch buffer1749.3 Example IMB sequences175Embedded Trace Macrocell Support17710.1 About Embedded Trace Macrocell support17810.1.1 FIFOFULL178Debug Support18111.1 About debug support18211.1.1 Debug clocks18211.1.2 Scan chain 15182Power Management18512.1 About power management18612.1.1 Dynamic power management (wait for interrupt mode)18612.1.2 Static power management (leakage control)187Signal Descriptions189A.1 Signal properties and requirements190A.2 AHB related signals191A.3 Coprocessor interface signals193A.4 Debug signals195A.5 JTAG signals197A.6 Miscellaneous signals198A.7 ETM interface signals200A.8 TCM interface signals202CP15 Test and Debug Registers207B.1 About the Test and Debug Registers208B.1.1 Debug Override Register208B.1.2 Debug and Test Address Register210B.1.3 Trace Control Register211B.1.4 MMU test operations211B.1.5 Cache Debug Control Register218B.1.6 MMU Debug Control Register219B.1.7 Memory Region Remap Register221Glossary225Index245A245B245C245D246E246F246H246I246J246L246M247N247O247P247R247S247T248U248V248W248Z248Dimensioni: 1,62 MBPagine: 248Language: EnglishApri il manuale
Scheda Tecnica (AT91SAM9N12-EK)SommarioSection 15Introduction51.1 SAM9N12/CN11 Evaluation Kit51.2 User Guide Content51.3 References and Applicable Documents5Section 26Kit Contents62.1 Deliverables62.2 Evaluation Board Specifications72.3 Electrostatic Warning7Section 38Power Up83.1 Power up the Board83.2 Battery83.3 Sample Code and Technical Support83.4 Recovery Procedure8Section 4 39Evaluation Kit Hardware94.1 Board Overview94.2 Equipment List104.2.1 Features List104.2.2 Interface Connection114.2.3 Configuration Items114.3 Function Blocks134.3.1 Processor134.3.2 Clock Distribution134.3.3 Reset and Wake-up Circuitry144.3.4 Power Supplies144.3.5 Power Rails154.3.6 Battery Backup164.3.7 Memory174.3.8 UART DBGU184.3.9 JTAG Interface184.3.10 Serial Peripheral Interface (SPI) Controller194.3.11 Two Wire Interface (TWI)194.3.12 USB Ports204.3.13 1-Wire EEPROM214.3.14 ETH on EBI214.3.15 Audio224.3.16 SD Card234.3.17 ZigBee Interface234.3.18 Analog Interface244.3.19 LED Indicators244.3.20 Push Buttons254.3.21 Expansion Ports264.3.22 PIO Usage274.4 Connectors314.4.1 Power Supply314.4.2 JTAG/ICE Connector314.4.3 DBGU324.4.4 USB MicroB334.4.5 USB Type A port334.4.6 SD Card MCI344.4.7 Ethernet RJ45 Socket354.4.8 Zigbee Socket J12354.4.9 LCD Socket364.4.10 IO Expansion Port38Section 541EK Schematics415.1 SAM9N12-EK Schematics415.2 SAM9CN11-EK Schematics51Section 661Display Module Hardware616.1 Board Overview616.2 Equipment List616.3 Function Blocks626.3.1 3.3V Regulator626.3.2 TFT LCD with Touch Panel626.3.3 Back Light636.3.4 QTouch646.3.5 1-Wire64Section 765DM Schematics657.1 DM Board Schematics65Section 867Revision History678.1 Revision History67Dimensioni: 3,36 MBPagine: 68Language: EnglishApri il manuale
Scheda Tecnica (AT91SAM9N12-EK)SommarioDescription11. Features22. Block Diagram43. Signal Description54. Package and Pinout94.1 Mechanical Overview of the 217-ball BGA Package94.2 Mechanical Overview of the 247-ball BGA Package104.3 217-ball BGA Package Pinout114.4 247-ball BGA Package Pinout175. Power Considerations235.1 Power Supplies236. Memories246.1 Memory Mapping256.2 Embedded Memories256.2.1 Internal SRAM256.2.2 Internal ROM256.3 External Memories Overview256.3.1 External Bus Interface256.3.2 Static Memory Controller256.3.3 DDR-SDRAM Controller266.3.4 Programmable Multi-bit Error Correcting Code (PMECC)266.3.5 Programmable Multi-bit ECC Error Location (PMERRLOC)267. System Controller277.1 System Controller Mapping277.2 System Controller Block DIagram287.3 Chip Identification297.4 Backup Section298. Peripherals308.1 Peripheral Mapping308.2 Peripheral Identifiers308.3 Peripheral Interrupts and Clock Control318.3.1 System Interrupt318.3.2 External Interrupts318.4 Peripheral Signal Multiplexing on I/O Lines318.4.1 Reset State318.4.2 PIO Line Selection328.5 Fuse Box Features328.5.1 Read328.5.2 Write329. ARM926EJ-S Processor Overview339.1 Description339.2 Embedded Characteristics339.3 Block Diagram359.4 ARM9EJ-S Processor369.4.1 ARM9EJ-S Operating States369.4.2 Switching State369.4.3 Instruction Pipelines369.4.4 Memory Access369.4.5 Jazelle Technology369.4.6 ARM9EJ-S Operating Modes379.4.7 ARM9EJ-S Registers379.4.7.1 Status Registers389.4.8 Exceptions399.4.8.1 Exception Types and Priorities399.4.8.2 Exception Modes and Handling399.4.9 ARM Instruction Set Overview409.4.10 New ARM Instruction Set419.4.11 Thumb Instruction Set Overview429.5 CP15 Coprocessor439.5.1 CP15 Registers Access449.6 Memory Management Unit (MMU)459.6.1 Access Control Logic459.6.2 Translation Look-aside Buffer (TLB)469.6.3 Translation Table Walk Hardware469.6.4 MMU Faults469.7 Caches and Write Buffer469.7.1 Instruction Cache (ICache)479.7.2 Data Cache (DCache) and Write Buffer479.7.2.1 DCache479.7.2.2 Write Buffer479.7.2.3 Write-though Operation479.7.2.4 Write-back Operation489.8 Bus Interface Unit489.8.1 Supported Transfers489.8.2 Thumb Instruction Fetches489.8.3 Address Alignment4810. Debug and Test4910.1 Description4910.2 Embedded Characteristics4910.3 Block Diagram5010.4 Application Examples5110.4.1 Debug Environment5110.4.2 Test Environment5210.5 Debug and Test Pin Description5210.6 Functional Description5310.6.1 EmbeddedICE5310.6.2 JTAG Signal Description5310.6.3 Debug Unit5310.6.4 IEEE 1149.1 JTAG Boundary Scan5410.6.5 JTAG ID Code Register5411. Advanced Interrupt Controller (AIC)5511.1 Description5511.2 Embedded Characteristics5511.3 Block Diagram5611.4 Application Block Diagram5611.5 AIC Detailed Block Diagram5611.6 I/O Line Description5711.7 Product Dependencies5711.7.1 I/O Lines5711.7.2 Power Management5711.7.3 Interrupt Sources5711.8 Functional Description5811.8.1 Interrupt Source Control5811.8.1.1 Interrupt Source Mode5811.8.1.2 Interrupt Source Enabling5811.8.1.3 Interrupt Clearing and Setting5811.8.1.4 Interrupt Status5811.8.2 Interrupt Latencies5911.8.3 Normal Interrupt6111.8.3.1 Priority Controller6111.8.3.2 Interrupt Nesting6111.8.3.3 Interrupt Vectoring6111.8.3.4 Interrupt Handlers6211.8.4 Fast Interrupt6311.8.4.1 Fast Interrupt Source6311.8.4.2 Fast Interrupt Control6311.8.4.3 Fast Interrupt Vectoring6311.8.4.4 Fast Interrupt Handlers6311.8.4.5 Fast Forcing6411.8.5 Protect Mode6511.8.6 Spurious Interrupt6511.8.7 General Interrupt Mask6611.9 Write Protection Registers6611.10 Advanced Interrupt Controller (AIC) User Interface6711.10.1 Base Address6711.10.2 AIC Source Mode Register6811.10.3 AIC Source Vector Register6911.10.4 AIC Interrupt Vector Register7011.10.5 AIC FIQ Vector Register7111.10.6 AIC Interrupt Status Register7211.10.7 AIC Interrupt Pending Register7311.10.8 AIC Interrupt Mask Register7411.10.9 AIC Core Interrupt Status Register7511.10.10 AIC Interrupt Enable Command Register7611.10.11 AIC Interrupt Disable Command Register7711.10.12 AIC Interrupt Clear Command Register7811.10.13 AIC Interrupt Set Command Register7911.10.14 AIC End of Interrupt Command Register8011.10.15 AIC Spurious Interrupt Vector Register8111.10.16 AIC Debug Control Register8211.10.17 AIC Fast Forcing Enable Register8311.10.18 AIC Fast Forcing Disable Register8411.10.19 AIC Fast Forcing Status Register8511.10.20 AIC Write Protect Mode Register8611.10.21 AIC Write Protect Status Register8712. Boot Strategies8812.1 SAM9CN12 only8812.2 SAM9CN11 and SAM9N12 only8812.2.1 ROM Code8812.2.2 Flow Diagram8912.2.3 Chip Setup8912.2.4 NVM Boot9012.2.4.1 NVM Boot Sequence9012.2.4.2 NVM Bootloader Program Description9212.2.4.3 Valid Code Detection9312.2.4.4 Detailed Memory Boot Procedures9412.2.4.5 Hardware and Software Constraints10112.2.5 SAM-BA Monitor10212.2.5.1 Command List10312.2.5.2 DBGU Serial Port10412.2.5.3 USB Device Port10513. Boot Sequence Controller (BSC)10613.1 Description10613.2 Embedded Characteristics10613.3 Product Dependencies10613.4 Boot Sequence Controller (BSC) Registers User Interface10713.4.1 Boot Sequence Configuration Register10714. Reset Controller (RSTC)10814.1 Description10814.2 Embedded Characteristics10814.3 Block Diagram10914.4 Functional Description11014.4.1 Reset Controller Overview11014.4.2 NRST Manager11014.4.2.1 NRST External Reset Control11114.4.3 BMS Sampling11114.4.4 Reset States11114.4.4.1 General Reset11114.4.4.2 Wake-up Reset11314.4.4.3 User Reset11414.4.4.4 Software Reset11514.4.4.5 Watchdog Reset11614.4.5 Reset State Priorities11714.4.6 Reset Controller Status Register11714.5 Reset Controller (RSTC) User Interface11814.5.1 Reset Controller Control Register11914.5.2 Reset Controller Status Register12014.5.3 Reset Controller Mode Register12115. Real-time Clock (RTC)12215.1 Description12215.2 Embedded Characteristics12215.3 Block Diagram12315.4 Product Dependencies12315.4.1 Power Management12315.4.2 Interrupt12315.5 Functional Description12415.5.1 Reference Clock12415.5.2 Timing12415.5.3 Alarm12415.5.4 Error Checking when Programming12415.5.5 Updating Time/Calendar12515.6 Real-time Clock (RTC) User Interface12715.6.1 RTC Control Register12815.6.2 RTC Mode Register12915.6.3 RTC Time Register13015.6.4 RTC Calendar Register13115.6.5 RTC Time Alarm Register13215.6.6 RTC Calendar Alarm Register13315.6.7 RTC Status Register13415.6.8 RTC Status Clear Command Register13515.6.9 RTC Interrupt Enable Register13615.6.10 RTC Interrupt Disable Register13715.6.11 RTC Interrupt Mask Register13815.6.12 RTC Valid Entry Register13916. Periodic Interval Timer (PIT)14016.1 Description14016.2 Embedded Characteristics14016.3 Block Diagram14116.4 Functional Description14216.5 Periodic Interval Timer (PIT) User Interface14316.5.1 Periodic Interval Timer Mode Register14416.5.2 Periodic Interval Timer Status Register14516.5.3 Periodic Interval Timer Value Register14616.5.4 Periodic Interval Timer Image Register14717. Watchdog Timer (WDT)14817.1 Description14817.2 Embedded Characteristics14817.3 Block Diagram14817.4 Functional Description14917.5 Watchdog Timer (WDT) User Interface15117.5.1 Watchdog Timer Control Register15217.5.2 Watchdog Timer Mode Register15317.5.3 Watchdog Timer Status Register15518. Shutdown Controller (SHDWC)15618.1 Description15618.2 Embedded Characteristics15618.3 Block Diagram15618.4 I/O Lines Description15618.5 Product Dependencies15718.5.1 Power Management15718.6 Functional Description15718.7 Shutdown Controller (SHDWC) User Interface15818.7.1 Shutdown Control Register15918.7.2 Shutdown Mode Register16018.7.3 Shutdown Status Register16119. General-Purpose Backup Registers (GPBR)16219.1 Description16219.2 Embedded Characteristics16219.3 General Purpose Backup Registers (GPBR) User Interface16219.3.1 General Purpose Backup Register x16220. Slow Clock Controller (SCKC)16320.1 Description16320.2 Embedded Characteristics16320.3 Block Diagram16320.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator16420.3.2 Bypass the 32768 Hz Oscillator16420.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator16420.4 Slow Clock Controller (SCKC) User Interface16520.4.1 Slow Clock Configuration Register16621. Clock Generator16721.1 Description16721.2 Embedded Characteristics16721.3 Block Diagram16821.4 Slow Clock Selection16921.4.1 Switch from Internal 32 kHz RC Oscillator to the 32,768 Hz Crystal16921.4.2 Bypass the 32768 Hz Oscillator17021.4.3 Switch from the 32,768 Hz Crystal to Internal 32 kHz RC Oscillator17021.4.4 Slow Clock Configuration Register17121.5 Main Clock17221.5.1 12 MHz Fast RC Oscillator17321.5.2 3 to 20 MHz Crystal Oscillator17321.5.3 Main Clock Oscillator Selection17321.5.4 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator17321.5.5 Software Sequence to Detect the Presence of Fast Crystal17421.5.6 Main Clock Frequency Counter17421.6 Divider and PLL Block17521.6.1 Divider and Phase Lock Loop Programming17522. Power Management Controller (PMC)17622.1 Description17622.2 Embedded Characteristics17622.3 Block Diagram17722.4 Master Clock Controller17722.5 Processor Clock Controller17822.6 USB Device and Host Clocks17822.7 LP-DDR/DDR2 Clock17822.8 Peripheral Clock Controller17922.9 Programmable Clock Output Controller17922.10 Programming Sequence18022.11 Clock Switching Details18322.11.1 Master Clock Switching Timings18322.11.2 Clock Switching Waveforms18422.12 Power Management Controller (PMC) User Interface18622.12.1 PMC System Clock Enable Register18722.12.2 PMC System Clock Disable Register18822.12.3 PMC System Clock Status Register18922.12.4 PMC Peripheral Clock Enable Register19022.12.5 PMC Peripheral Clock Disable Register19122.12.6 PMC Peripheral Clock Status Register19222.12.7 PMC Clock Generator Main Oscillator Register19322.12.8 PMC Clock Generator Main Clock Frequency Register19422.12.9 PMC Clock Generator PLLA Register19522.12.10 PMC Clock Generator PLLB Register19622.12.11 PMC Master Clock Register19722.12.12 USB Clock Register19922.12.13 PMC Programmable Clock Register20022.12.14 PMC Interrupt Enable Register20122.12.15 PMC Interrupt Disable Register20222.12.16 PMC Status Register20322.12.17 PMC Interrupt Mask Register20522.12.18 PLL Charge Pump Current Register20622.12.19 PMC Write Protect Mode Register20722.12.20 PMC Write Protect Status Register20822.12.21 PMC Peripheral Control Register20923. Parallel Input/Output Controller (PIO)21023.1 Description21023.2 Embedded Characteristics21023.3 Block Diagram21123.4 Product Dependencies21223.4.1 Pin Multiplexing21223.4.2 External Interrupt Lines21223.4.3 Power Management21223.4.4 Interrupt Generation21223.5 Functional Description21323.5.1 Pull-up and Pull-down Resistor Control21423.5.2 I/O Line or Peripheral Function Selection21423.5.3 Peripheral A or B or C or D Selection21423.5.4 Output Control21523.5.5 Synchronous Data Output21523.5.6 Multi-Drive Control (Open Drain)21523.5.7 Output Line Timings21523.5.8 Inputs21623.5.9 Input Glitch and Debouncing Filters21623.5.10 Input Edge/Level Interrupt21723.5.10.1 Example21823.5.10.2 Interrupt Mode Configuration21923.5.10.3 Edge or Level Detection Configuration21923.5.10.4 Falling/Rising Edge or Low/High-Level Detection Configuration21923.5.11 Programmable I/O Delays21923.5.12 Programmable I/O Drive22023.5.13 Programmable Schmitt Trigger22023.5.14 Register Write Protection22023.6 I/O Lines Programming Example22123.7 Parallel Input/Output Controller (PIO) User Interface22223.7.1 PIO Enable Register22423.7.2 PIO Disable Register22423.7.3 PIO Status Register22523.7.4 PIO Output Enable Register22623.7.5 PIO Output Disable Register22623.7.6 PIO Output Status Register22723.7.7 PIO Input Filter Enable Register22823.7.8 PIO Input Filter Disable Register22823.7.9 PIO Input Filter Status Register22923.7.10 PIO Set Output Data Register23023.7.11 PIO Clear Output Data Register23023.7.12 PIO Output Data Status Register23123.7.13 PIO Pin Data Status Register23223.7.14 PIO Interrupt Enable Register23323.7.15 PIO Interrupt Disable Register23323.7.16 PIO Interrupt Mask Register23423.7.17 PIO Interrupt Status Register23523.7.18 PIO Multi-driver Enable Register23623.7.19 PIO Multi-driver Disable Register23623.7.20 PIO Multi-driver Status Register23723.7.21 PIO Pull-Up Disable Register23823.7.22 PIO Pull-Up Enable Register23823.7.23 PIO Pull-Up Status Register23923.7.24 PIO Peripheral ABCD Select Register 124023.7.25 PIO Peripheral ABCD Select Register 224123.7.26 PIO Input Filter Slow Clock Disable Register24223.7.27 PIO Input Filter Slow Clock Enable Register24223.7.28 PIO Input Filter Slow Clock Status Register24323.7.29 PIO Slow Clock Divider Debouncing Register24423.7.30 PIO Pad Pull-Down Disable Register24523.7.31 PIO Pad Pull-Down Enable Register24523.7.32 PIO Pad Pull-Down Status Register24623.7.33 PIO Output Write Enable Register24723.7.34 PIO Output Write Disable Register24723.7.35 PIO Output Write Status Register24823.7.36 PIO Additional Interrupt Modes Enable Register24923.7.37 PIO Additional Interrupt Modes Disable Register24923.7.38 PIO Additional Interrupt Modes Mask Register25023.7.39 PIO Edge Select Register25123.7.40 PIO Level Select Register25123.7.41 PIO Edge/Level Status Register25223.7.42 PIO Falling Edge/Low-Level Select Register25223.7.43 PIO Rising Edge/High-Level Select Register25323.7.44 PIO Fall/Rise - Low/High Status Register25323.7.45 PIO Write Protection Mode Register25423.7.46 PIO Write Protection Status Register25523.7.47 PIO Schmitt Trigger Register25623.7.48 PIO I/O Delay Register25723.7.49 PIO I/O Drive Register 125823.7.50 PIO I/O Drive Register 225924. Debug Unit (DBGU)26024.1 Description26024.2 Embedded Characteristics26024.3 Block Diagram26124.4 Product Dependencies26224.4.1 I/O Lines26224.4.2 Power Management26224.4.3 Interrupt Source26224.5 UART Operations26224.5.1 Baud Rate Generator26224.5.2 Receiver26324.5.2.1 Receiver Reset, Enable and Disable26324.5.2.2 Start Detection and Data Sampling26324.5.2.3 Receiver Ready26424.5.2.4 Receiver Overrun26424.5.2.5 Parity Error26424.5.2.6 Receiver Framing Error26524.5.3 Transmitter26524.5.3.1 Transmitter Reset, Enable and Disable26524.5.3.2 Transmit Format26524.5.3.3 Transmitter Control26524.5.4 DMA Support26624.5.5 Test Modes26624.5.6 Debug Communication Channel Support26724.5.7 Chip Identifier26824.5.8 ICE Access Prevention26824.6 Debug Unit (DBGU) User Interface26924.6.1 Debug Unit Control Register27024.6.2 Debug Unit Mode Register27124.6.3 Debug Unit Interrupt Enable Register27224.6.4 Debug Unit Interrupt Disable Register27324.6.5 Debug Unit Interrupt Mask Register27424.6.6 Debug Unit Status Register27524.6.7 Debug Unit Receiver Holding Register27624.6.8 Debug Unit Transmit Holding Register27624.6.9 Debug Unit Baud Rate Generator Register27724.6.10 Debug Unit Chip ID Register27824.6.11 Debug Unit Chip ID Extension Register28224.6.12 Debug Unit Force NTRST Register28325. Fuse Controller (FUSE)28425.1 Description28425.2 Embedded Characteristics28425.3 Block Diagram28425.4 Functional Description28525.4.1 Fuse Reading28525.4.2 Fuse Programming28525.4.3 Fuse Masking28625.5 Fuse Controller (FUSE) User Interface28725.5.1 Fuse Control Register28825.5.2 Fuse Mode Register28925.5.3 Fuse Index Register29025.5.4 Fuse Data Register29125.5.5 Fuse Status Register29226. Bus Matrix (MATRIX)29326.1 Description29326.2 Embedded Characteristics29326.3 Matrix Masters29426.4 Matrix Slaves29426.5 Master to Slave Access29426.6 Memory Mapping29526.7 Special Bus Granting Mechanism29526.7.1 No Default Master29526.7.2 Last Access Master29526.7.3 Fixed Default Master29526.8 Arbitration29626.8.1 Arbitration Scheduling29626.8.1.1 Undefined Length Burst Arbitration29626.8.1.2 Slot Cycle Limit Arbitration29726.8.2 Arbitration Priority Scheme29726.8.2.1 Fixed Priority Arbitration29826.8.2.2 Round-Robin Arbitration29826.9 Write Protect Registers29826.10 Bus Matrix (MATRIX) User Interface29926.10.1 Bus Matrix Master Configuration Registers30026.10.2 Bus Matrix Slave Configuration Registers30126.10.3 Bus Matrix Priority Registers A For Slaves30226.10.4 Bus Matrix Master Remap Control Register30326.10.5 Chip Configuration User Interface30426.10.5.1 EBI Chip Select Assignment Register30526.10.6 Write Protect Mode Register30726.10.7 Write Protect Status Register30827. External Bus Interface (EBI)30927.1 Description30927.2 Embedded Characteristics30927.3 EBI Block Diagram31027.4 I/O Lines Description31127.5 Application Example31227.5.1 Hardware Interface31227.5.2 Connection Examples31427.6 Product Dependencies31527.6.1 I/O Lines31527.7 Functional Description31527.7.1 Bus Multiplexing31527.7.2 Pull-up Control31527.7.3 Drive level31527.7.4 Power Supplies31627.7.5 Static Memory Controller31827.7.6 DDR2SDRAM Controller31827.7.7 Programmable Multi-bit ECC Controller31827.7.8 NAND Flash Support31827.7.8.1 External Bus Interface31827.7.8.2 NAND Flash Signals31927.8 Implementation Examples32027.8.1 2x8-bit DDR2 on EBI32027.8.1.1 Hardware Configuration32027.8.1.2 Software Configuration32027.8.2 16-bit LPDDR on EBI32127.8.2.1 Hardware Configuration32127.8.2.2 Software Configuration32127.8.3 16-bit SDRAM32227.8.3.1 Hardware Configuration32227.8.3.2 Software Configuration32227.8.4 2x16-bit SDRAM32327.8.4.1 Hardware Configuration32327.8.4.2 Software Configuration32327.8.5 8-bit NAND Flash with NFD0_ON_D16 = 032427.8.5.1 Hardware Configuration32427.8.5.2 Software Configuration32427.8.6 16-bit NAND Flash with NFD0_ON_D16 = 032527.8.6.1 Hardware Configuration32527.8.6.2 Software Configuration32527.8.7 8-bit NAND Flash with NFD0_ON_D16 = 132627.8.7.1 Hardware Configuration32627.8.7.2 Software Configuration32627.8.8 16-bit NAND Flash with NFD0_ON_D16 = 132727.8.8.1 Hardware Configuration32727.8.8.2 Software Configuration32727.8.9 NOR Flash on NCS032827.8.9.1 Hardware Configuration32827.8.9.2 Software Configuration32828. Programmable Multibit ECC Controller (PMECC)32928.1 Description32928.2 Embedded Characteristics32928.3 Block Diagram33028.4 Functional Description33128.4.1 MLC/SLC Write Page Operation using PMECC33328.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set33428.4.1.2 MLC/SLC Write Operation with Spare Area Disabled33428.4.2 MLC/SLC Read Page Operation using PMECC33528.4.2.1 MLC/SLC Read Operation with Spare Decoding33528.4.2.2 MLC/SLC Read Operation33628.4.2.3 MLC/SLC User Read ECC Area33628.5 Software Implementation33728.5.1 Remainder Substitution Procedure33728.5.2 Find the Error Location Polynomial Sigma(x)33828.5.3 Find the Error Position34028.6 Programmable Multibit ECC Controller (PMECC) User Interface34128.6.1 PMECC Configuration Register34328.6.2 PMECC Spare Area Size Register34528.6.3 PMECC Start Address Register34628.6.4 PMECC End Address Register34728.6.5 PMECC Clock Control Register34828.6.6 PMECC Control Register34928.6.7 PMECC Status Register35028.6.8 PMECC Interrupt Enable Register35128.6.9 PMECC Interrupt Disable Register35228.6.10 PMECC Interrupt Mask Register35328.6.11 PMECC Interrupt Status Register35428.6.12 PMECC ECC x Register35528.6.13 PMECC Remainder x Register35629. Programmable Multibit ECC Error Location Controller (PMERRLOC)35729.1 Description35729.2 Embedded Characteristics35729.3 Block Diagram35729.4 Functional Description35829.5 Programmable Multibit ECC Error Location (PMERRLOC) User Interface35929.5.1 Error Location Configuration Register36029.5.2 Error Location Primitive Register36129.5.3 Error Location Enable Register36229.5.4 Error Location Disable Register36329.5.5 Error Location Status Register36429.5.6 Error Location Interrupt Enable Register36529.5.7 Error Location Interrupt Disable Register36629.5.8 Error Location Interrupt Mask Register36729.5.9 Error Location Interrupt Status Register36829.5.10 Error Location SIGMAx Register36929.5.11 PMECC Error Locationx Register37030. Static Memory Controller (SMC)37130.1 Description37130.2 Embedded Characteristics37130.3 I/O Lines Description37230.4 Multiplexed Signals37230.5 Application Example37330.5.1 Hardware Interface37330.6 Product Dependencies37330.6.1 I/O Lines37330.7 External Memory Mapping37430.8 Connection to External Devices37430.8.1 Data Bus Width37430.8.2 Byte Write or Byte Select Access37530.8.2.1 Byte Write Access37630.8.2.2 Byte Select Access37630.8.2.3 Signal Multiplexing37730.9 Standard Read and Write Protocols37830.9.1 Read Waveforms37830.9.1.1 NRD Waveform37830.9.1.2 NCS Waveform37830.9.1.3 Read Cycle37930.9.1.4 Null Delay Setup and Hold37930.9.1.5 Null Pulse37930.9.2 Read Mode38030.9.2.1 Read is Controlled by NRD (READ_MODE = 1):38030.9.2.2 Read is Controlled by NCS (READ_MODE = 0)38130.9.3 Write Waveforms38230.9.3.1 NWE Waveforms38230.9.3.2 NCS Waveforms38230.9.3.3 Write Cycle38330.9.3.4 Null Delay Setup and Hold38330.9.3.5 Null Pulse38330.9.4 Write Mode38430.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)38430.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)38430.9.5 Write Protected Registers38530.9.6 Coding Timing Parameters38530.9.7 Reset Values of Timing Parameters38530.9.8 Usage Restriction38530.10 Automatic Wait States38630.10.1 Chip Select Wait States38630.10.2 Early Read Wait State38730.10.3 Reload User Configuration Wait State38930.10.3.1 User Procedure38930.10.3.2 Slow Clock Mode Transition38930.10.4 Read to Write Wait State38930.11 Data Float Wait States39030.11.1 READ_MODE39030.11.2 TDF Optimization Enabled (TDF_MODE = 1)39130.11.3 TDF Optimization Disabled (TDF_MODE = 0)39230.12 External Wait39430.12.1 Restriction39430.12.2 Frozen Mode39530.12.3 Ready Mode39730.12.4 NWAIT Latency and Read/Write Timings39930.13 Slow Clock Mode40030.13.1 Slow Clock Mode Waveforms40030.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode40130.14 Asynchronous Page Mode40230.14.1 Protocol and Timings in Page Mode40230.14.2 Byte Access Type in Page Mode40330.14.3 Page Mode Restriction40330.14.4 Sequential and Non-sequential Accesses40330.15 Programmable IO Delays40530.16 Static Memory Controller (SMC) User Interface40630.16.1 SMC Setup Register40730.16.2 SMC Pulse Register40830.16.3 SMC Cycle Register40930.16.4 SMC MODE Register41030.16.5 SMC DELAY I/O Register41230.16.6 SMC Write Protect Mode Register41330.16.7 SMC Write Protect Status Register41431. DDR SDR SDRAM Controller (DDRSDRC)41531.1 Description41531.2 Embedded Characteristics41631.3 DDRSDRC Module Diagram41731.4 Initialization Sequence41831.4.1 SDR-SDRAM Initialization41831.4.2 Low-power DDR1-SDRAM Initialization41931.4.3 DDR2-SDRAM Initialization42031.5 Functional Description42231.5.1 SDRAM Controller Write Cycle42231.5.2 SDRAM Controller Read Cycle42731.5.3 Refresh (Auto-refresh Command)43131.5.4 Power Management43131.5.4.1 Self-refresh Mode43131.5.4.2 Power-down Mode43431.5.4.3 Deep Power-down Mode43531.5.4.4 Reset Mode43631.5.5 Multi-port Functionality43631.5.6 Write Protected Registers43831.6 Software Interface/SDRAM Organization, Address Mapping43931.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks43931.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks44131.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width44131.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface44331.7.1 DDRSDRC Mode Register44431.7.2 DDRSDRC Refresh Timer Register44531.7.3 DDRSDRC Configuration Register44631.7.4 DDRSDRC Timing Parameter 0 Register44931.7.5 DDRSDRC Timing Parameter 1 Register45131.7.6 DDRSDRC Timing Parameter 2 Register45231.7.7 DDRSDRC Low-power Register45331.7.8 DDRSDRC Memory Device Register45531.7.9 DDRSDRC DLL Register45631.7.10 DDRSDRC High Speed Register45731.7.11 DDRSDRC Write Protect Mode Register45831.7.12 DDRSDRC Write Protect Status Register45932. DMA Controller (DMAC)46032.1 Description46032.2 Embedded Characteristics46032.3 DMA Controller Peripheral Connections46132.4 Block Diagram46232.5 Functional Description46332.5.1 Basic Definitions46332.5.2 Memory Peripherals46632.5.3 Handshaking Interface46632.5.3.1 Software Handshaking46632.5.4 DMAC Transfer Types46732.5.4.1 Multi-buffer Transfers46732.5.4.2 Programming DMAC for Multiple Buffer Transfers46932.5.4.3 Ending Multi-buffer Transfers47032.5.5 Programming a Channel47032.5.5.1 Programming Examples47032.5.6 Disabling a Channel Prior to Transfer Completion48732.5.6.1 Abnormal Transfer Termination48732.6 DMAC Software Requirements48832.7 Write Protection Registers48932.8 DMA Controller (DMAC) User Interface49032.8.1 DMAC Global Configuration Register49132.8.2 DMAC Enable Register49232.8.3 DMAC Software Single Request Register49332.8.4 DMAC Software Chunk Transfer Request Register49432.8.5 DMAC Software Last Transfer Flag Register49532.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register49632.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register49732.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register49832.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register49932.8.10 DMAC Channel Handler Enable Register50032.8.11 DMAC Channel Handler Disable Register50132.8.12 DMAC Channel Handler Status Register50232.8.13 DMAC Channel x [x = 0..7] Source Address Register50332.8.14 DMAC Channel x [x = 0..7] Destination Address Register50432.8.15 DMAC Channel x [x = 0..7] Descriptor Address Register50532.8.16 DMAC Channel x [x = 0..7] Control A Register50632.8.17 DMAC Channel x [x = 0..7] Control B Register50832.8.18 DMAC Channel x [x = 0..7] Configuration Register51032.8.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register51232.8.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register51332.8.21 DMAC Write Protect Mode Register51432.8.22 DMAC Write Protect Status Register51533. USB Device Port (UDP)51633.1 Description51633.2 Embedded Characteristics51633.3 Block Diagram51733.3.1 Signal Description51733.4 Product Dependencies51833.4.1 I/O Lines51833.4.2 Power Management51833.4.3 Interrupt51833.5 Typical Connection51933.5.1 USB Device Transceiver51933.5.2 VBUS Monitoring51933.6 Functional Description52033.6.1 USB V2.0 Full-speed Introduction52033.6.1.1 USB V2.0 Full-speed Transfer Types52033.6.1.2 USB Bus Transactions52033.6.1.3 USB Transfer Event Definitions52133.6.2 Handling Transactions with USB V2.0 Device Peripheral52333.6.2.1 Setup Transaction52333.6.2.2 Data IN Transaction52333.6.2.3 Data OUT Transaction52633.6.2.4 Stall Handshake52933.6.2.5 Transmit Data Cancellation53033.6.3 Controlling Device States53133.6.3.1 Not Powered State53133.6.3.2 Entering Attached State53233.6.3.3 From Powered State to Default State53233.6.3.4 From Default State to Address State53233.6.3.5 From Address State to Configured State53233.6.3.6 Entering in Suspend State53233.6.3.7 Receiving a Host Resume53333.6.3.8 Sending a Device Remote Wakeup53333.7 USB Device Port (UDP) User Interface53433.7.1 UDP Frame Number Register53533.7.2 UDP Global State Register53633.7.3 UDP Function Address Register53733.7.4 UDP Interrupt Enable Register53833.7.5 UDP Interrupt Disable Register53933.7.6 UDP Interrupt Mask Register54033.7.7 UDP Interrupt Status Register54133.7.8 UDP Interrupt Clear Register54333.7.9 UDP Reset Endpoint Register54433.7.10 UDP Endpoint Control and Status Register (Control, Bulk Interrupt Endpoints)54533.7.11 UDP Endpoint Control and Status Register (Isochronous Endpoints)55033.7.12 UDP FIFO Data Register55433.7.13 UDP Transceiver Control Register55534. USB Host Port (UHP)55634.1 Description55634.2 Embedded Characteristics55634.3 Block Diagram55734.4 Product Dependencies55834.4.1 I/O Lines55834.4.2 Power Management55834.4.3 Interrupt55834.5 Functional Description55934.5.1 Host Controller Interface55934.5.2 Host Controller Driver56034.6 Typical Connection56035. High Speed MultiMedia Card Interface (HSMCI)56135.1 Description56135.2 Embedded Characteristics56135.3 Block Diagram56235.4 Application Block Diagram56335.5 Pin Name List56335.6 Product Dependencies56435.6.1 I/O Lines56435.6.2 Power Management56435.6.3 Interrupt56435.7 Bus Topology56435.8 High Speed MultiMedia Card Operations56735.8.1 Command - Response Operation56735.8.2 Data Transfer Operation57035.8.3 Read Operation57135.8.4 Write Operation57235.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller57535.8.6 READ_SINGLE_BLOCK Operation using DMA Controller57635.8.6.1 Block Length is Multiple of 457635.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)57735.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)57835.8.7 WRITE_MULTIPLE_BLOCK57935.8.7.1 One Block per Descriptor57935.8.8 READ_MULTIPLE_BLOCK58035.8.8.1 Block Length is a Multiple of 458035.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)58135.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)58335.9 SD/SDIO Card Operation58435.9.1 SDIO Data Transfer Type58435.9.2 SDIO Interrupts58535.10 CE-ATA Operation58535.10.1 Executing an ATA Polling Command58535.10.2 Executing an ATA Interrupt Command58535.10.3 Aborting an ATA Command58535.10.4 CE-ATA Error Recovery58535.11 HSMCI Boot Operation Mode58635.11.1 Boot Procedure, Processor Mode58635.11.2 Boot Procedure DMA Mode58635.12 HSMCI Transfer Done Timings58735.12.1 Definition58735.12.2 Read Access58735.12.3 Write Access58735.13 Register Write Protection58835.14 High Speed MultiMedia Card Interface (HSMCI) User Interface58935.14.1 HSMCI Control Register59035.14.2 HSMCI Mode Register59135.14.3 HSMCI Data Timeout Register59235.14.4 HSMCI SDCard/SDIO Register59335.14.5 HSMCI Argument Register59435.14.6 HSMCI Command Register59535.14.7 HSMCI Block Register59735.14.8 HSMCI Completion Signal Timeout Register59835.14.9 HSMCI Response Register59935.14.10 HSMCI Receive Data Register60035.14.11 HSMCI Transmit Data Register60135.14.12 HSMCI Status Register60235.14.13 HSMCI Interrupt Enable Register60535.14.14 HSMCI Interrupt Disable Register60735.14.15 HSMCI Interrupt Mask Register60935.14.16 HSMCI DMA Configuration Register61135.14.17 HSMCI Configuration Register61235.14.18 HSMCI Write Protection Mode Register61335.14.19 HSMCI Write Protection Status Register61435.14.20 HSMCI FIFOx Memory Aperture61536. Serial Peripheral Interface (SPI)61636.1 Description61636.2 Embedded Characteristics61636.3 Block Diagram61736.4 Application Block Diagram61836.5 Signal Description61836.6 Product Dependencies61936.6.1 I/O Lines61936.6.2 Power Management61936.6.3 Interrupt61936.6.4 Direct Memory Access Controller (DMAC)61936.7 Functional Description62036.7.1 Modes of Operation62036.7.2 Data Transfer62036.7.3 Master Mode Operations62236.7.3.1 Master Mode Block Diagram62336.7.3.2 Master Mode Flow Diagram62436.7.3.3 Clock Generation62536.7.3.4 Transfer Delays62536.7.3.5 Peripheral Selection62636.7.3.6 SPI Direct Access Memory Controller (DMAC)62636.7.3.7 Peripheral Chip Select Decoding62736.7.3.8 Peripheral Deselection without DMA62836.7.3.9 Peripheral Deselection with DMAC62836.7.3.10 Mode Fault Detection62936.7.4 SPI Slave Mode63036.7.5 Write Protected Registers63136.8 Serial Peripheral Interface (SPI) User Interface63236.8.1 SPI Control Register63336.8.2 SPI Mode Register63436.8.3 SPI Receive Data Register63636.8.4 SPI Transmit Data Register63736.8.5 SPI Status Register63836.8.6 SPI Interrupt Enable Register63936.8.7 SPI Interrupt Disable Register64036.8.8 SPI Interrupt Mask Register64136.8.9 SPI Chip Select Register64236.8.10 SPI Write Protection Mode Register64436.8.11 SPI Write Protection Status Register64537. Timer Counter (TC)64637.1 Description64637.2 Embedded Characteristics64637.3 Block Diagram64737.4 Pin Name List64837.5 Product Dependencies64837.5.1 I/O Lines64837.5.2 Power Management64837.5.3 Interrupt64837.6 Functional Description64937.6.1 TC Description64937.6.2 32-bit Counter64937.6.3 Clock Selection64937.6.4 Clock Control65137.6.5 TC Operating Modes65137.6.6 Trigger65137.6.7 Capture Operating Mode65237.6.8 Capture Registers A and B65237.6.9 Transfer with DMAC65237.6.10 Trigger Conditions65337.6.11 Waveform Operating Mode65537.6.12 Waveform Selection65537.6.12.1 WAVSEL = 0065737.6.12.2 WAVSEL = 1065837.6.12.3 WAVSEL = 0165937.6.12.4 WAVSEL = 1166037.6.13 External Event/Trigger Conditions66137.6.14 Output Controller66137.7 Timer Counter (TC) User Interface66237.7.1 TC Channel Control Register66337.7.2 TC Channel Mode Register: Capture Mode66437.7.3 TC Channel Mode Register: Waveform Mode66637.7.4 TC Register AB67037.7.5 TC Counter Value Register67137.7.6 TC Register A67237.7.7 TC Register B67337.7.8 TC Register C67437.7.9 TC Status Register67537.7.10 TC Interrupt Enable Register67737.7.11 TC Interrupt Disable Register67837.7.12 TC Interrupt Mask Register67937.7.13 TC Block Control Register68037.7.14 TC Block Mode Register68138. Pulse Width Modulation Controller (PWM)68238.1 Description68238.2 Embedded characteristics68238.3 Block Diagram68338.4 I/O Lines Description68338.5 Product Dependencies68438.5.1 I/O Lines68438.5.2 Power Management68438.5.3 Interrupt Sources68438.6 Functional Description68538.6.1 PWM Clock Generator68538.6.2 PWM Channel68638.6.2.1 Block Diagram68638.6.2.2 Waveform Properties68638.6.3 PWM Controller Operations68938.6.3.1 Initialization68938.6.3.2 Source Clock Selection Criteria68938.6.3.3 Changing the Duty Cycle or the Period68938.6.3.4 Interrupts69038.7 Pulse Width Modulation Controller (PWM) User Interface69138.7.1 PWM Mode Register69238.7.2 PWM Enable Register69338.7.3 PWM Disable Register69438.7.4 PWM Status Register69538.7.5 PWM Interrupt Enable Register69638.7.6 PWM Interrupt Disable Register69738.7.7 PWM Interrupt Mask Register69838.7.8 PWM Interrupt Status Register69938.7.9 PWM Channel Mode Register70038.7.10 PWM Channel Duty Cycle Register70138.7.11 PWM Channel Period Register70238.7.12 PWM Channel Counter Register70338.7.13 PWM Channel Update Register70439. Two-wire Interface (TWI)70539.1 Description70539.2 Embedded Characteristics70639.3 List of Abbreviations70639.4 Block Diagram70739.5 Application Block Diagram70739.5.1 I/O Lines Description70739.6 Product Dependencies70839.6.1 I/O Lines70839.6.2 Power Management70839.6.3 Interrupt70839.7 Functional Description70939.7.1 Transfer Format70939.7.2 Modes of Operation70939.8 Master Mode71039.8.1 Definition71039.8.2 Application Block Diagram71039.8.3 Programming Master Mode71039.8.4 Master Transmitter Mode71039.8.5 Master Receiver Mode71239.8.6 Internal Address71439.8.6.1 7-bit Slave Addressing71439.8.6.2 10-bit Slave Addressing71539.8.7 Using the DMA Controller71539.8.7.1 Data Transmit with the DMA71539.8.7.2 Data Receive with the DMA71639.8.8 SMBUS Quick Command (Master Mode Only)71639.8.9 Read-write Flowcharts71739.9 Multi-master Mode72339.9.1 Definition72339.9.2 Different Multi-master Modes72339.9.2.1 TWI as Master Only72339.9.2.2 TWI as Master or Slave72339.10 Slave Mode72639.10.1 Definition72639.10.2 Application Block Diagram72639.10.3 Programming Slave Mode72639.10.4 Receiving Data72639.10.4.1 Read Sequence72639.10.4.2 Write Sequence72739.10.4.3 Clock Synchronization Sequence72739.10.4.4 General Call72739.10.5 Data Transfer72739.10.5.1 Read Operation72739.10.5.2 Write Operation72839.10.5.3 General Call72839.10.5.4 Clock Synchronization72939.10.5.5 Reversal after a Repeated Start73039.10.6 Using the DMA Controller73139.10.6.1 Data Transmit with the DMA73139.10.6.2 Data Receive with the DMA73139.10.7 Read Write Flowcharts73239.11 Write Protection System73339.12 Two-wire Interface (TWI) User Interface73439.12.1 TWI Control Register73539.12.2 TWI Master Mode Register73739.12.3 TWI Slave Mode Register73839.12.4 TWI Internal Address Register73939.12.5 TWI Clock Waveform Generator Register74039.12.6 TWI Status Register74139.12.7 TWI Interrupt Enable Register74439.12.8 TWI Interrupt Disable Register74539.12.9 TWI Interrupt Mask Register74639.12.10 TWI Receive Holding Register74739.12.11 TWI Transmit Holding Register74839.12.12 TWI Write Protection Mode Register74939.12.13 TWI Write Protection Status Register75040. Universal Synchronous Asynchronous Receiver Transceiver (USART)75140.1 Description75140.2 Embedded Characteristics75140.3 Block Diagram75340.4 Application Block Diagram75440.5 I/O Lines Description75540.6 Product Dependencies75540.6.1 I/O Lines75540.6.2 Power Management75640.6.3 Interrupt75640.7 Functional Description75740.7.1 Baud Rate Generator75840.7.1.1 Baud Rate in Asynchronous Mode75840.7.1.2 Fractional Baud Rate in Asynchronous Mode75940.7.1.3 Baud Rate in Synchronous Mode or SPI Mode76040.7.1.4 Baud Rate in ISO 7816 Mode76040.7.2 Receiver and Transmitter Control76240.7.3 Synchronous and Asynchronous Modes76240.7.3.1 Transmitter Operations76240.7.3.2 Manchester Encoder76340.7.3.3 Asynchronous Receiver76540.7.3.4 Manchester Decoder76640.7.3.5 Radio Interface: Manchester Encoded USART Application76840.7.3.6 Synchronous Receiver76940.7.3.7 Receiver Operations77040.7.3.8 Parity77040.7.3.9 Multidrop Mode77140.7.3.10 Transmitter Timeguard77140.7.3.11 Receiver Time-out77240.7.3.12 Framing Error77440.7.3.13 Transmit Break77440.7.3.14 Receive Break77540.7.3.15 Hardware Handshaking77540.7.4 ISO7816 Mode77640.7.4.1 ISO7816 Mode Overview77640.7.4.2 Protocol T = 077640.7.4.3 Protocol T = 177840.7.5 IrDA Mode77840.7.5.1 IrDA Modulation77840.7.5.2 IrDA Baud Rate77940.7.5.3 IrDA Demodulator78040.7.6 RS485 Mode78040.7.7 SPI Mode78140.7.7.1 Modes of Operation78140.7.7.2 Baud Rate78240.7.7.3 Data Transfer78240.7.7.4 Receiver and Transmitter Control78540.7.7.5 Character Transmission78540.7.7.6 Character Reception78540.7.7.7 Receiver Timeout78540.7.8 LIN Mode78640.7.8.1 Modes of Operation78640.7.8.2 Baud Rate Configuration78640.7.8.3 Receiver and Transmitter Control78640.7.8.4 Character Transmission78640.7.8.5 Character Reception78640.7.8.6 Header Transmission (Master Node Configuration)78640.7.8.7 Header Reception (Slave Node Configuration)78740.7.8.8 Slave Node Synchronization78840.7.8.9 Identifier Parity79040.7.8.10 Node Action79040.7.8.11 Response Data Length79140.7.8.12 Checksum79140.7.8.13 Frame Slot Mode79140.7.8.14 LIN Errors79240.7.8.15 LIN Frame Handling79340.7.8.16 LIN Frame Handling With the DMAC79740.7.8.17 Wake-up Request79840.7.8.18 Bus Idle Time-out79940.7.9 Test Modes79940.7.9.1 Normal Mode79940.7.9.2 Automatic Echo Mode80040.7.9.3 Local Loopback Mode80040.7.9.4 Remote Loopback Mode80040.7.10 Write Protection Registers80140.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface80240.8.1 USART Control Register80340.8.2 USART Control Register (SPI_MODE)80540.8.3 USART Mode Register80740.8.4 USART Mode Register (SPI_MODE)81040.8.5 USART Interrupt Enable Register81240.8.6 USART Interrupt Enable Register (SPI_MODE)81340.8.7 USART Interrupt Enable Register (LIN_MODE)81440.8.8 USART Interrupt Disable Register81540.8.9 USART Interrupt Disable Register (SPI_MODE)81640.8.10 USART Interrupt Disable Register (LIN_MODE)81740.8.11 USART Interrupt Mask Register81840.8.12 USART Interrupt Mask Register (SPI_MODE)81940.8.13 USART Interrupt Mask Register (LIN_MODE)82040.8.14 USART Channel Status Register82140.8.15 USART Channel Status Register (SPI_MODE)82340.8.16 USART Channel Status Register (LIN_MODE)82440.8.17 USART Receive Holding Register82740.8.18 USART Transmit Holding Register82840.8.19 USART Baud Rate Generator Register82940.8.20 USART Receiver Time-out Register83040.8.21 USART Transmitter Timeguard Register83140.8.22 USART FI DI RATIO Register83240.8.23 USART Number of Errors Register83340.8.24 USART IrDA FILTER Register83440.8.25 USART Manchester Configuration Register83540.8.26 USART LIN Mode Register83740.8.27 USART LIN Identifier Register83940.8.28 USART LIN Baud Rate Register84040.8.29 USART Write Protect Mode Register84140.8.30 USART Write Protect Status Register84241. Universal Asynchronous Receiver Transmitter (UART)84341.1 Description84341.2 Embedded Characteristics84341.3 Block Diagram84441.4 Product Dependencies84541.4.1 I/O Lines84541.4.2 Power Management84541.4.3 Interrupt Source84541.5 UART Operations84541.5.1 Baud Rate Generator84541.5.2 Receiver84641.5.2.1 Receiver Reset, Enable and Disable84641.5.2.2 Start Detection and Data Sampling84641.5.2.3 Receiver Ready84741.5.2.4 Receiver Overrun84741.5.2.5 Parity Error84741.5.2.6 Receiver Framing Error84841.5.3 Transmitter84841.5.3.1 Transmitter Reset, Enable and Disable84841.5.3.2 Transmit Format84841.5.3.3 Transmitter Control84941.5.4 DMA Support84941.5.5 Test Modes84941.6 Universal Asynchronous Receiver Transmitter (UART) User Interface85141.6.1 UART Control Register85241.6.2 UART Mode Register85341.6.3 UART Interrupt Enable Register85441.6.4 UART Interrupt Disable Register85541.6.5 UART Interrupt Mask Register85641.6.6 UART Status Register85741.6.7 UART Receiver Holding Register85841.6.8 UART Transmit Holding Register85941.6.9 UART Baud Rate Generator Register86042. Analog-to-Digital Converter (ADC)86142.1 Description86142.2 Embedded Characteristics86242.3 Block Diagram86342.4 Signal Description86342.5 Product Dependencies86442.5.1 Power Management86442.5.2 Interrupt Sources86442.5.3 Analog Inputs86442.5.4 I/O Lines86442.5.5 Timer Triggers86442.5.6 Conversion Performance86442.6 Functional Description86542.6.1 Analog-to-digital Conversion86542.6.2 Conversion Reference86542.6.3 Conversion Resolution86542.6.4 Conversion Results86642.6.5 Conversion Triggers86842.6.6 Sleep Mode and Conversion Sequencer86842.6.7 Comparison Window86942.6.8 ADC Timings86942.7 Touchscreen87042.7.1 Touchscreen Mode87042.7.2 4-wire Resistive Touchscreen Principles87042.7.3 4-wire Position Measurement Method87142.7.4 4-wire Pressure Measurement Method87242.7.5 5-wire Resistive Touchscreen Principles87242.7.6 5-wire Position Measurement Method87342.7.7 Sequence and Noise Filtering87542.7.8 Measured Values, Registers and Flags87542.7.9 Pen Detect Method87642.7.10 Buffer Structure87742.7.10.1 Classical ADC Channels Only87742.7.10.2 Touchscreen Channels Only87842.7.10.3 Interleaved Channels88042.7.10.4 Pen Detection Status88242.7.11 Write Protected Registers88342.8 Analog-to-Digital Converter (ADC) User Interface88442.8.1 ADC Control Register88542.8.2 ADC Mode Register88642.8.3 ADC Channel Sequence 1 Register88842.8.4 ADC Channel Sequence 2 Register88942.8.5 ADC Channel Enable Register89042.8.6 ADC Channel Disable Register89142.8.7 ADC Channel Status Register89242.8.8 ADC Last Converted Data Register89342.8.9 ADC Interrupt Enable Register89442.8.10 ADC Interrupt Disable Register89542.8.11 ADC Interrupt Mask Register89642.8.12 ADC Interrupt Status Register89742.8.13 ADC Overrun Status Register89942.8.14 ADC Extended Mode Register90042.8.15 ADC Compare Window Register90142.8.16 ADC Channel Data Register90242.8.17 ADC Analog Control Register90342.8.18 ADC Touchscreen Mode Register90442.8.19 ADC Touchscreen X Position Register90642.8.20 ADC Touchscreen Y Position Register90742.8.21 ADC Touchscreen Pressure Register90842.8.22 ADC Trigger Register90942.8.23 ADC Write Protect Mode Register91042.8.24 ADC Write Protect Status Register91143. Synchronous Serial Controller (SSC)91243.1 Description91243.2 Embedded Characteristics91243.3 Block Diagram91343.4 Application Block Diagram91343.5 Pin Name List91443.6 Product Dependencies91443.6.1 I/O Lines91443.6.2 Power Management91443.6.3 Interrupt91443.7 Functional Description91543.7.1 Clock Management91643.7.1.1 Clock Divider91643.7.1.2 Transmitter Clock Management91743.7.1.3 Receiver Clock Management91843.7.1.4 Serial Clock Ratio Considerations91843.7.2 Transmitter Operations91943.7.3 Receiver Operations92043.7.4 Start92043.7.5 Frame Sync92243.7.5.1 Frame Sync Data92243.7.5.2 Frame Sync Edge Detection92243.7.6 Receive Compare Modes92243.7.6.1 Compare Functions92343.7.7 Data Format92343.7.8 Loop Mode92543.7.9 Interrupt92543.8 SSC Application Examples92643.8.1 Write Protection Registers92843.9 Synchronous Serial Controller (SSC) User Interface92943.9.1 SSC Control Register93043.9.2 SSC Clock Mode Register93143.9.3 SSC Receive Clock Mode Register93243.9.4 SSC Receive Frame Mode Register93443.9.5 SSC Transmit Clock Mode Register93643.9.6 SSC Transmit Frame Mode Register93843.9.7 SSC Receive Holding Register94043.9.8 SSC Transmit Holding Register94143.9.9 SSC Receive Synchronization Holding Register94243.9.10 SSC Transmit Synchronization Holding Register94343.9.11 SSC Receive Compare 0 Register94443.9.12 SSC Receive Compare 1 Register94543.9.13 SSC Status Register94643.9.14 SSC Interrupt Enable Register94843.9.15 SSC Interrupt Disable Register94943.9.16 SSC Interrupt Mask Register95043.9.17 SSC Write Protect Mode Register95143.9.18 SSC Write Protect Status Register95244. LCD Controller (LCDC)95344.1 Description95344.2 Embedded Characteristics95344.3 Block Diagram95444.4 I/O Lines Description95544.5 Product Dependencies95544.5.1 I/O Lines95544.5.2 Power Management95644.5.3 Interrupt Sources95644.6 Functional Description95744.6.1 Timing Engine Configuration95744.6.1.1 Pixel Clock Period Configuration95744.6.1.2 Horizontal and Vertical Synchronization Configuration95744.6.1.3 Timing Engine Power Up Software Operation95744.6.1.4 Timing Engine Power Down Software Operation95844.6.2 DMA Software Operations95844.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure95844.6.2.2 Programming a DMA Channel95844.6.2.3 Disabling a DMA channel95844.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor95844.6.2.5 DMA Interrupt Generation95944.6.2.6 DMA Address Alignment Requirements95944.6.3 Display Software Configuration95944.6.3.1 System Bus Access Attributes95944.6.3.2 Color Attributes96044.6.3.3 Window Attributes Software Operation96044.6.4 RGB Frame Buffer Memory Bitmap96044.6.4.1 1 bpp Through Color Lookup Table96044.6.4.2 2 bpp Through Color Lookup Table96044.6.4.3 4 bpp Through Color Lookup Table96044.6.4.4 8 bpp Through Color Lookup Table96044.6.4.5 12 bpp Memory Mapping, RGB 4:4:496044.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:496144.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:496144.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:596144.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:596144.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:696144.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:696144.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:696244.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:696244.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:896244.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:896344.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:896344.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:896344.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:896344.6.5 Output Timing Generation96444.6.5.1 Active Display Timing Mode96444.6.6 Output Format96844.6.6.1 Active Mode Output Pin Assignment96844.7 LCD Controller (LCDC) User Interface96944.7.1 LCD Controller Configuration Register 097144.7.2 LCD Controller Configuration Register 197244.7.3 LCD Controller Configuration Register 297344.7.4 LCD Controller Configuration Register 397444.7.5 LCD Controller Configuration Register 497544.7.6 LCD Controller Configuration Register 597644.7.7 LCD Controller Configuration Register 697844.7.8 LCD Controller Enable Register97944.7.9 LCD Controller Disable Register98044.7.10 LCD Controller Status Register98144.7.11 LCD Controller Interrupt Enable Register98244.7.12 LCD Controller Interrupt Disable Register98344.7.13 LCD Controller Interrupt Mask Register98444.7.14 LCD Controller Interrupt Status Register98544.7.15 Base Layer Channel Enable Register98644.7.16 Base Layer Channel Disable Register98744.7.17 Base Layer Channel Status Register98844.7.18 Base Layer Interrupt Enable Register98944.7.19 Base Layer Interrupt Disable Register99044.7.20 Base Layer Interrupt Mask Register99144.7.21 Base Layer Interrupt Status Register99244.7.22 Base Layer Head Register99344.7.23 Base Layer Address Register99444.7.24 Base Layer Control Register99544.7.25 Base Layer Next Register99644.7.26 Base Layer Configuration 0 Register99744.7.27 Base Layer Configuration 1 Register99844.7.28 Base Layer Configuration 2 Register99944.7.29 Base Layer Configuration 3 Register100044.7.30 Base Layer Configuration 4 Register100144.7.31 Base CLUT Register x Register100245. Advanced Encryption Standard (AES)100345.1 Description100345.2 Embedded Characteristics100345.3 Product Dependencies100345.3.1 Power Management100345.3.2 Interrupt100345.4 Functional Description100445.4.1 Operation Modes100445.4.2 Double Input Buffer100445.4.3 Start Modes100545.4.3.1 Manual Mode100545.4.3.2 Auto Mode100545.4.3.3 DMA Mode100545.4.4 Last Output Data Mode100645.4.4.1 Manual and Auto Modes100645.4.4.2 DMA Mode100745.5 Security Features100945.5.1 Unspecified Register Access Detection100945.6 Advanced Encryption Standard (AES) User Interface101045.6.1 AES Control Register101145.6.2 AES Mode Register101245.6.3 AES Interrupt Enable Register101445.6.4 AES Interrupt Disable Register101545.6.5 AES Interrupt Mask Register101645.6.6 AES Interrupt Status Register101745.6.7 AES Key Word Register x101845.6.8 AES Input Data Register x101945.6.9 AES Output Data Register x102045.6.10 AES Initialization Vector Register x102146. Secure Hash Algorithm (SHA)102246.1 Description102246.2 Embedded Characteristics102246.3 Product Dependencies102246.3.1 Power Management102246.3.2 Interrupt102246.4 Functional Description102346.4.1 SHA Algorithm102346.4.2 Processing Period102346.4.3 Double Input Buffer102346.4.4 Start Modes102346.4.4.1 Manual Mode102346.4.4.2 Auto Mode102446.4.4.3 DMA Mode102446.4.4.4 SHA Register Endianism102446.4.5 Security Features102546.5 Secure Hash Algorithm (SHA) User Interface102646.5.1 SHA Control Register102746.5.2 SHA Mode Register102846.5.3 SHA Interrupt Enable Register102946.5.4 SHA Interrupt Disable Register103046.5.5 SHA Interrupt Mask Register103146.5.6 SHA Interrupt Status Register103246.5.7 SHA Input Data x Register103346.5.8 SHA Output Data x Register103447. True Random Number Generator (TRNG)103547.1 Description103547.2 Embedded Characteristics103547.3 Block Diagram103547.4 Product Dependencies103547.4.1 Power Management103547.4.2 Interrupt103547.5 Functional Description103647.6 True Random Number Generator (TRNG) User Interface103747.6.1 TRNG Control Register103847.6.2 TRNG Interrupt Enable Register103947.6.3 TRNG Interrupt Disable Register104047.6.4 TRNG Interrupt Mask Register104147.6.5 TRNG Interrupt Status Register104247.6.6 TRNG Output Data Register104348. Electrical Characteristics104448.1 Absolute Maximum Ratings104448.2 DC Characteristics104448.3 Power Consumption104648.3.1 Power Consumption versus Modes104648.4 Clock Characteristics104748.4.1 Processor Clock104748.4.2 System Clock104748.4.3 Main Oscillator Characteristics104848.4.4 Crystal Oscillator Characteristics104948.4.5 XIN Clock Characteristics104948.5 12 MHz RC Oscillator Characteristics105048.6 32 kHz Oscillator Characteristics105048.6.1 32 kHz Crystal Characteristics105148.6.2 XIN32 Clock Characteristics105148.7 32 kHz RC Oscillator Characteristics105148.8 PLL Characteristics105248.9 I/Os105248.10 Analog-to-Digital Converter (ADC)105348.11 USB Transceiver Characteristics105448.11.1 Electrical Characteristics105448.12 Core Power Supply POR Characteristics105548.12.1 Power Sequence Requirements105548.12.2 Power-Up Sequence105548.13 SMC Timings105648.13.1 Timing Conditions105648.13.2 Timing Extraction105648.13.2.1 Zero Hold Mode Restrictions105648.13.2.2 Read Timings105748.13.2.3 Write Timings105848.14 DDRSDRC Timings106048.15 Peripheral Timings106048.15.1 SPI106048.15.1.1 Maximum SPI Frequency106048.15.1.2 Timing Conditions106148.15.1.3 Timing Extraction106148.15.2 SSC106448.15.2.1 Timing conditions106448.15.2.2 Timing Extraction106548.15.3 HSMCI106948.15.4 USART in SPI Mode Timings106948.15.4.1 Timing conditions106948.15.4.2 Timing extraction106948.15.5 UDP107149. Mechanical Overview of the 217-ball and 247-ball BGA Packages107249.1 217-ball BGA Package107249.2 247-ball BGA Package107449.3 Marking107550. SAM9N12/SAM9CN11/SAM9CN12 Ordering Information107651. SAM9N/CN Series Errata107751.1 SAM9N12/CN11/CN12 Errata107751.1.1 Reset Controller (RSTC)107751.1.1.1 RSTC: Reset during SDRAM Accesses107751.1.2 LCD Controller (LCDC)107751.1.2.1 LCDC: LCDC PWM Is Not Usable107751.1.3 12 MHz RC Oscillator107751.1.3.1 Reset Hangs with 12 MHz RC Disabled107751.2 SAM9CN12 Errata: Revision A107851.2.1 BootROM107851.2.1.1 Boot from SPI Serial Flash Devices (xx25xxx) Is not Working107851.2.2 16 MHz Main Crystal107851.2.2.1 16 MHz Main Crystal Detection107851.3 SAM9CN12 Errata: Revision B107851.3.1 Boot ROM107851.3.1.1 Boot from SPI Data/Serial Flash Devices do not work with All Memories1078Revision History1079Table of Contents1095Dimensioni: 4,76 MBPagine: 1104Language: EnglishApri il manuale