Manuale Utente (CM8062307262003)SommarioIntroduction9Intel® Xeon® Processor E3-1200 Family Platform10Processor Feature Details111.1.1 Supported Technologies11Interfaces111.2.1 System Memory Support111.2.2 PCI Express*12PCIe Supported Configurations in Server/Workstation Products121.2.3 Direct Media Interface (DMI)141.2.4 Platform Environment Control Interface (PECI)141.2.5 Processor Graphics151.2.6 Intel® Flexible Display Interface (Intel® FDI)15Power Management Support161.3.1 Processor Core161.3.2 System161.3.3 Memory Controller161.3.4 PCI Express*161.3.5 DMI161.3.6 Processor Graphics Controller16Thermal Management Support16Package17Terminology17Related Documents19Related Documents19Interfaces21System Memory Interface212.1.1 System Memory Technology Supported21Supported UDIMM Module Configurations212.1.2 System Memory Timing Support22DDR3 System Memory Timing Support222.1.3 System Memory Organization Modes232.1.3.1 Single-Channel Mode232.1.3.2 Dual-Channel Mode Intel® Flex Memory Technology Mode23Intel® Flex Memory Technology Operation232.1.4 Rules for Populating Memory Slots242.1.5 Technology Enhancements of Intel ® Fast Memory Access (Intel® FMA)242.1.5.1 Just-in-Time Command Scheduling242.1.5.2 Command Overlap242.1.5.3 Out-of-Order Scheduling252.1.6 Memory Type Range Registers (MTRRs) Enhancement252.1.7 Data Scrambling25PCI Express* Interface252.2.1 PCI Express* Architecture25PCI Express* Layering Diagram26Packet Flow through the Layers262.2.1.1 Transaction Layer272.2.1.2 Data Link Layer272.2.1.3 Physical Layer272.2.2 PCI Express* Configuration Mechanism282.2.3 PCI Express* Port28PCI Express* Related Register Structures in the Processor282.2.4 PCI Express Lanes Connection29Direct Media Interface (DMI)292.3.1 DMI Error Flow292.3.2 Processor/PCH Compatibility Assumptions29PCIe Typical Operation 16 lanes Mapping292.3.3 DMI Link Down30Processor Graphics Controller (GT)30Processor Graphics Controller Unit Block Diagram302.4.1 3D and Video Engines for Graphics Processing312.4.1.1 3D Engine Execution Units312.4.1.2 3D Pipeline312.4.1.3 Video Engine322.4.1.4 2D Engine322.4.2 Processor Graphics Display332.4.2.1 Display Planes33Processor Display Block Diagram332.4.2.2 Display Pipes342.4.2.3 Display Ports342.4.3 Intel® Flexible Display Interface342.4.4 Multi-Graphics Controller Multi-Monitor Support34Platform Environment Control Interface (PECI)35Interface Clocking352.6.1 Internal Clocking Requirements35Reference Clock353.1 Intel® Virtualization Technology373.1.1 Intel® VT-x Objectives373.1.2 Intel® VT-x Features383.1.3 Intel® VT-d Objectives383.1.4 Intel® VT-d Features383.1.5 Intel® VT-d Features Not Supported393.2 Intel® Trusted Execution Technology (Intel ® TXT)403.3 Intel® Hyper-Threading Technology403.4 Intel® Turbo Boost Technology413.4.1 Intel® Turbo Boost Technology Frequency413.4.2 Intel® Turbo Boost Technology Graphics Frequency413.5 Intel® Advanced Vector Extensions (AVX)423.6 Advanced Encryption Standard New Instructions (AES-NI)423.6.1 PCLMULQDQ Instruction423.7 Intel® 64 Architecture x2APIC42Power States454.1 Advanced Configuration and Power Interface (ACPI) States Supported464.1.1 System States464.1.2 Processor Core/Package Idle States464.1.3 Integrated Memory Controller States464.1.4 PCIe Link States46System States46Processor Core/Package State Support46Integrated Memory Controller States46PCIe Link States464.1.5 DMI States474.1.6 Processor Graphics Controller States474.1.7 Interface State Combinations47DMI States47Processor Graphics Controller States47G, S, and C State Combinations474.2 Processor Core Power Management484.2.1 Enhanced Intel® SpeedStep® Technology484.2.2 Low-Power Idle States48Idle Power Management Breakdown of the Processor Cores49Thread and Core C-State Entry and Exit494.2.3 Requesting Low-Power Idle States50Coordination of Thread Power States at the Core Level50P_LVLx to MWAIT Conversion504.2.4 Core C-states514.2.4.1 Core C0 State514.2.4.2 Core C1/C1E State514.2.4.3 Core C3 State514.2.4.4 Core C6 State514.2.4.5 C-State Auto-Demotion514.2.5 Package C-States52Coordination of Core Power States at the Package Level524.2.5.1 Package C0534.2.5.2 Package C1/C1E53Package C-State Entry and Exit534.2.5.3 Package C3 State544.2.5.4 Package C6 State544.3 IMC Power Management544.3.1 Disabling Unused System Memory Outputs544.3.2 DRAM Power Management and Initialization554.3.2.1 Initialization Role of CKE564.3.2.2 Conditional Self-Refresh564.3.2.3 Dynamic Power-down Operation574.3.2.4 DRAM I/O Power Management57PCIe* Power Management57DMI Power Management57Graphics Power Management58(also known as CxSR)584.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)584.6.3 Graphics Render C-State584.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)584.6.5 Intel® Graphics Dynamic Frequency59Thermal Power Management59Thermal Management61Signal Description63Signal Description Buffer Types63System Memory Interface64Memory Channel A64Memory Reference and Compensation65Memory Channel B65Memory Reference and Compensation65Reset and Miscellaneous Signals66Reset and Miscellaneous Signals66PCI Express* Based Interface Signals67Intel® Flexible Display Interface Signals67DMI67PCI Express* Graphics Interface Signals67Intel® Flexible Display Interface67DMI - Processor to PCH Serial Interface67PLL Signals68TAP Signals68PLL Signals68TAP Signals68Error and Thermal Protection696.10 Power Sequencing69Error and Thermal Protection69Power Sequencing696.11 Processor Power Signals706.12 Sense Pins706.13 Ground and NCTF70Processor Power Signals70Sense Pins70Ground and NCTF706.14 Processor Internal Pull Up/Pull Down71Processor Internal Pull Up/Pull Down71Electrical Specifications73Power and Ground Lands73Decoupling Guidelines737.2.1 Voltage Rail Decoupling73Processor Clocking (BCLK[0], BCLK#[0])747.3.1 PLL Power Supply74VCC Voltage Identification (VID)74VR 12.0 Voltage Identification Definition75System Agent (SA) VCC VID78Reserved or Unused Signals78VCCSA_VID configuration78Signal Groups79Signal Groups 179Test Access Port (TAP) Connection80Storage Conditions Specifications81Storage Condition Ratings817.10 DC Specifications827.10.1 Voltage and Current Specifications82Processor Core Active and Idle Mode DC Voltage and Current Specifications82Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications83Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications84DDR3 Signal Group DC Specifications84Control Sideband and TAP Signal Group DC Specifications85PCIe DC Specifications867.11 Platform Environmental Control Interface (PECI) DC Specifications877.11.1 PECI Bus Architecture87Example for PECI Host-clients Connection877.11.2 DC Characteristics887.11.3 Input Device Hysteresis88Input Device Hysteresis88PECI DC Electrical Limits88Processor Pin and Signal Information898.1 Processor Pin Assignments89Socket Pinmap (Top View, Upper-Left Quadrant)90Socket Pinmap (Top View, Upper-Right Quadrant)91Socket Pinmap (Top View, Lower-Left Quadrant)92Socket Pinmap (Top View, Lower-Right Quadrant)93Processor Pin List by Pin Name94DDR Data Swizzling109DDR Data Swizzling Table Channel A110DDR Data Swizzling Table Channel B111Dimensioni: 2,14 MBPagine: 112Language: EnglishApri il manuale