Инструкции для Intel E3-1275

Содержание

• Introduction

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• Intel® Xeon® Processor E3-1200 Family Platform

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• Processor Feature Details

  11
• 1.1.1 Supported Technologies

  11
• Interfaces

  11
• 1.2.1 System Memory Support

  11
• 1.2.2 PCI Express*

  12
• PCIe Supported Configurations in Server/Workstation Products

  12
• 1.2.3 Direct Media Interface (DMI)

  14
• 1.2.4 Platform Environment Control Interface (PECI)

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• 1.2.5 Processor Graphics

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• 1.2.6 Intel® Flexible Display Interface (Intel® FDI)

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• Power Management Support

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• 1.3.1 Processor Core

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• 1.3.2 System

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• 1.3.3 Memory Controller

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• 1.3.4 PCI Express*

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• 1.3.5 DMI

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• 1.3.6 Processor Graphics Controller

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• Thermal Management Support

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• Package

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• Terminology

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• Related Documents

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• Related Documents

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• Interfaces

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• System Memory Interface

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• 2.1.1 System Memory Technology Supported

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• Supported UDIMM Module Configurations

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• 2.1.2 System Memory Timing Support

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• DDR3 System Memory Timing Support

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• 2.1.3 System Memory Organization Modes

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• 2.1.3.1 Single-Channel Mode

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• 2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

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• Intel® Flex Memory Technology Operation

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• 2.1.4 Rules for Populating Memory Slots

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• 2.1.5 Technology Enhancements of Intel ® Fast Memory Access (Intel® FMA)

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• 2.1.5.1 Just-in-Time Command Scheduling

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• 2.1.5.2 Command Overlap

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• 2.1.5.3 Out-of-Order Scheduling

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• 2.1.6 Memory Type Range Registers (MTRRs) Enhancement

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• 2.1.7 Data Scrambling

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• PCI Express* Interface

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• 2.2.1 PCI Express* Architecture

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• PCI Express* Layering Diagram

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• Packet Flow through the Layers

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• 2.2.1.1 Transaction Layer

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• 2.2.1.2 Data Link Layer

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• 2.2.1.3 Physical Layer

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• 2.2.2 PCI Express* Configuration Mechanism

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• 2.2.3 PCI Express* Port

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• PCI Express* Related Register Structures in the Processor

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• 2.2.4 PCI Express Lanes Connection

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• Direct Media Interface (DMI)

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• 2.3.1 DMI Error Flow

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• 2.3.2 Processor/PCH Compatibility Assumptions

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• PCIe Typical Operation 16 lanes Mapping

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• 2.3.3 DMI Link Down

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• Processor Graphics Controller (GT)

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• Processor Graphics Controller Unit Block Diagram

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• 2.4.1 3D and Video Engines for Graphics Processing

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• 2.4.1.1 3D Engine Execution Units

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• 2.4.1.2 3D Pipeline

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• 2.4.1.3 Video Engine

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• 2.4.1.4 2D Engine

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• 2.4.2 Processor Graphics Display

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• 2.4.2.1 Display Planes

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• Processor Display Block Diagram

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• 2.4.2.2 Display Pipes

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• 2.4.2.3 Display Ports

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• 2.4.3 Intel® Flexible Display Interface

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• 2.4.4 Multi-Graphics Controller Multi-Monitor Support

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• Platform Environment Control Interface (PECI)

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• Interface Clocking

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• 2.6.1 Internal Clocking Requirements

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• Reference Clock

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• 3.1 Intel® Virtualization Technology

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• 3.1.1 Intel® VT-x Objectives

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• 3.1.2 Intel® VT-x Features

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• 3.1.3 Intel® VT-d Objectives

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• 3.1.4 Intel® VT-d Features

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• 3.1.5 Intel® VT-d Features Not Supported

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• 3.2 Intel® Trusted Execution Technology (Intel ® TXT)

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• 3.3 Intel® Hyper-Threading Technology

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• 3.4 Intel® Turbo Boost Technology

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• 3.4.1 Intel® Turbo Boost Technology Frequency

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• 3.4.2 Intel® Turbo Boost Technology Graphics Frequency

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• 3.5 Intel® Advanced Vector Extensions (AVX)

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• 3.6 Advanced Encryption Standard New Instructions (AES-NI)

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• 3.6.1 PCLMULQDQ Instruction

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• 3.7 Intel® 64 Architecture x2APIC

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• Power States

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• 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

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• 4.1.1 System States

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• 4.1.2 Processor Core/Package Idle States

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• 4.1.3 Integrated Memory Controller States

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• 4.1.4 PCIe Link States

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• System States

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• Processor Core/Package State Support

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• Integrated Memory Controller States

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• PCIe Link States

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• 4.1.5 DMI States

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• 4.1.6 Processor Graphics Controller States

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• 4.1.7 Interface State Combinations

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• DMI States

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• Processor Graphics Controller States

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• G, S, and C State Combinations

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• 4.2 Processor Core Power Management

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• 4.2.1 Enhanced Intel® SpeedStep® Technology

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• 4.2.2 Low-Power Idle States

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• Idle Power Management Breakdown of the Processor Cores

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• Thread and Core C-State Entry and Exit

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• 4.2.3 Requesting Low-Power Idle States

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• Coordination of Thread Power States at the Core Level

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• P_LVLx to MWAIT Conversion

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• 4.2.4 Core C-states

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• 4.2.4.1 Core C0 State

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• 4.2.4.2 Core C1/C1E State

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• 4.2.4.3 Core C3 State

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• 4.2.4.4 Core C6 State

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• 4.2.4.5 C-State Auto-Demotion

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• 4.2.5 Package C-States

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• Coordination of Core Power States at the Package Level

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• 4.2.5.1 Package C0

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• 4.2.5.2 Package C1/C1E

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• Package C-State Entry and Exit

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• 4.2.5.3 Package C3 State

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• 4.2.5.4 Package C6 State

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• 4.3 IMC Power Management

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• 4.3.1 Disabling Unused System Memory Outputs

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• 4.3.2 DRAM Power Management and Initialization

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• 4.3.2.1 Initialization Role of CKE

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• 4.3.2.2 Conditional Self-Refresh

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• 4.3.2.3 Dynamic Power-down Operation

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• 4.3.2.4 DRAM I/O Power Management

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• PCIe* Power Management

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• DMI Power Management

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• Graphics Power Management

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• (also known as CxSR)

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• 4.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)

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• 4.6.3 Graphics Render C-State

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• 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

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• 4.6.5 Intel® Graphics Dynamic Frequency

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• Thermal Power Management

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• Thermal Management

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• Signal Description

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• Signal Description Buffer Types

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• System Memory Interface

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• Memory Channel A

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• Memory Reference and Compensation

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• Memory Channel B

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• Memory Reference and Compensation

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• Reset and Miscellaneous Signals

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• Reset and Miscellaneous Signals

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• PCI Express* Based Interface Signals

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• Intel® Flexible Display Interface Signals

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• DMI

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• PCI Express* Graphics Interface Signals

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• Intel® Flexible Display Interface

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• DMI - Processor to PCH Serial Interface

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• PLL Signals

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• TAP Signals

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• PLL Signals

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• TAP Signals

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• Error and Thermal Protection

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• 6.10 Power Sequencing

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• Error and Thermal Protection

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• Power Sequencing

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• 6.11 Processor Power Signals

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• 6.12 Sense Pins

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• 6.13 Ground and NCTF

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• Processor Power Signals

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• Sense Pins

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• Ground and NCTF

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• 6.14 Processor Internal Pull Up/Pull Down

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• Processor Internal Pull Up/Pull Down

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• Electrical Specifications

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• Power and Ground Lands

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• Decoupling Guidelines

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• 7.2.1 Voltage Rail Decoupling

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• Processor Clocking (BCLK[0], BCLK#[0])

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• 7.3.1 PLL Power Supply

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• VCC Voltage Identification (VID)

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• VR 12.0 Voltage Identification Definition

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• System Agent (SA) VCC VID

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• Reserved or Unused Signals

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• VCCSA_VID configuration

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• Signal Groups

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• Signal Groups 1

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• Test Access Port (TAP) Connection

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• Storage Conditions Specifications

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• Storage Condition Ratings

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• 7.10 DC Specifications

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• 7.10.1 Voltage and Current Specifications

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• Processor Core Active and Idle Mode DC Voltage and Current Specifications

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• Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications

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• Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications

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• DDR3 Signal Group DC Specifications

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• Control Sideband and TAP Signal Group DC Specifications

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• PCIe DC Specifications

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• 7.11 Platform Environmental Control Interface (PECI) DC Specifications

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• 7.11.1 PECI Bus Architecture

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• Example for PECI Host-clients Connection

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• 7.11.2 DC Characteristics

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• 7.11.3 Input Device Hysteresis

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• Input Device Hysteresis

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• PECI DC Electrical Limits

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• Processor Pin and Signal Information

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• 8.1 Processor Pin Assignments

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• Socket Pinmap (Top View, Upper-Left Quadrant)

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• Socket Pinmap (Top View, Upper-Right Quadrant)

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• Socket Pinmap (Top View, Lower-Left Quadrant)

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• Socket Pinmap (Top View, Lower-Right Quadrant)

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• Processor Pin List by Pin Name

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• DDR Data Swizzling

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• DDR Data Swizzling Table – Channel A

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• DDR Data Swizzling Table – Channel B

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