Scheda Tecnica (MRF49XA-I/ST)SommarioFeatures3RF/Analog Features3Baseband Features3Typical Applications3Pin Diagram: 16-Pin TSSOP4Table of Contents5Most Current Data Sheet5Errata5Customer Notification System51.0 Introduction7FIGURE 1-1: Functional Node Block Diagram8FIGURE 1-2: Microcontroller to MRF49XA Interface82.0 Hardware Description9FIGURE 2-1: MRF49XA Architectural Block Diagram10TABLE 2-1: Pin Description (Continued)112.1 Power and Ground Pins13TABLE 2-2: Recommended Bypass Capacitors Value13TABLE 2-3: Recommended Bypass Capacitors132.2 RESET Pin132.3 Power Amplifier132.4 Low Noise Amplifier132.5 RFXTL/EXTREF and CLKOUT Pins142.6 Phase-Locked Loop142.7 Automatic Frequency Control142.8 Baseband/Data Filters142.9 Clock Recovery Circuit142.10 Data Validity Blocks152.10.1 Receive Signal Strength Indicator152.10.2 Data Quality Indicator152.10.3 Data Indicator Output15FIGURE 2-2: Analog RSSI Voltage vs. RF Input Power152.11 Power-Saving Blocks162.11.1 Low Battery Voltage Detector162.11.2 Wake-up Timer162.11.3 Low Duty Cycle mode162.12 INT, IRO Pins and Interrupts162.13 Transmit Register162.14 Receive FIFO172.15 Serial Peripheral Interface172.16 Memory Organization18TABLE 2-4: Control (Command) Register Description182.17 Control (Command) Register Details19Register 2-1: STSREG: Status Read Register (POR: 0x0000)(1) (Continued)19Register 2-2: GENCREG: General Configuration Register (POR: 0x8008)21Register 2-3: AFCCREG: Automatic Frequency Control Configuration Register (POR: 0xC4F7)22Register 2-4: TXCREG: Transmit Configuration Register (POR: 0x9800) (Continued)23EQUATION 2-1:24Register 2-5: TXBREG: Transmit Byte Register (POR: 0xB8AA)25Register 2-6: CFSREG: Center Frequency Value Set Register (POR: 0xA680)26EQUATION 2-2:26TABLE 2-5: Center Frequency Value26TABLE 2-6: Frequency Band Tuning Resolution26Register 2-7: RXCREG: Receive Control Register (POR: 0x9080) (Continued)27Register 2-8: BBFCREG: Baseband Filter Configuration Register (POR: 0xC22C)29EQUATION 2-3:30TABLE 2-7: Data Rate vs. Filter Capacitor Value30Register 2-9: RXFIFOREG: Receiver FIFO Read Register (POR: 0xB000)31Register 2-10: FIFORSTREG: FIFO and Reset Mode Configuration Register (POR: 0xCA80)32TABLE 2-8: Synchronous Character Selection33TABLE 2-9: Reset Mode Selection33Register 2-11: SYNBREG: Synchronous Byte Configuration Register (POR: 0xCED4)34Register 2-12: DRSREG: Data Rate Value Set Register (POR: 0xC623)35EQUATION 2-4:35EQUATION 2-5:35EQUATION 2-6:35Register 2-13: PMCREG: Power Management Configuration Register (POR: 0x8208) (Continued)36Register 2-14: WTSREG: Wake-up Timer Value Set Register (POR: 0xE196)38EQUATION 2-7:38Register 2-15: DCSREG: Duty Cycle Value Set Register (POR: 0xC80E)39EQUATION 2-8:39Register 2-16: BCSREG: Battery Threshold Detect and Clock Output Value Set Register (POR: 0xC000)40EQUATION 2-9:40Register 2-17: PLLCREG: PLL Configuration Register (POR: 0xCC77)41TABLE 2-10: Control/Command Register Map423.0 Functional Description433.1 Reset433.1.1 Power-on Reset43FIGURE 3-1: Power-on Reset Example433.1.2 Power Glitch Reset44FIGURE 3-2: Sensitive Reset Enabled44FIGURE 3-3: Sensitive Reset Disabled453.1.3 Software Reset453.1.4 Reset Pin45FIGURE 3-4: RESET Pin Internal Connection453.2 Vdd Line Filtering463.3 Power and Low Noise Amplifiers473.4 Crystal Oscillator and Clock Output47TABLE 3-1: Programmable Load Capacitance Value473.4.1 Clock Tail Feature473.4.2 Auto Crystal Oscillator483.5 Phase-Locked Loop483.6 Crystal Selection Guidelines49FIGURE 3-5: Maximum Crystal Tolerances Including Temperature and Aging (ppm)493.7 Automatic Frequency Control50FIGURE 3-6: AFC Circuit for Frequency Offset Correction513.8 Initialization523.9 Interrupts523.9.1 Setting Interrupts533.9.2 Clearing Interrupts53FIGURE 3-7: MRF49XA Interrupt Generation Logic553.10 Baseband/Data Filtering56FIGURE 3-8: Full Baseband Amplifier Transfer Function (BW = 67 kHz)56EXAMPLE 3-1: Frequency Deviation and BBBW Calculation56FIGURE 3-9: FSK Modulated Deviation – Maximum TX TO RX Offset573.10.1 Analog Filtering Mode573.10.2 Digital Filtering Mode573.11 Data Quality Indicator58EQUATION 3-1:58FIGURE 3-10: DIO Logic Block Diagram583.12 Programmable Synchronous Byte593.13 Received Signal Strength Indicator59EQUATION 3-2:59TABLE 3-2: Digital RSSI Threshold Levels60FIGURE 3-11: Input Power vs. Analog RSSI Voltage603.13.1 Relationship Between RSSI and Clock Recovery603.13.2 Relationship Between RSSI and AFC603.14 Power Management61FIGURE 3-12: Logic Connections Between Power Control Bits633.15 Low Duty Cycle Mode64EQUATION 3-3:64FIGURE 3-13: Low-Power Duty Cycle Mode Sequence643.16 Sleep, Wake-up and Battery Operations65EQUATION 3-4:65EQUATION 3-5:653.17 TX Register Buffered Data Transmission66EQUATION 3-6:66FIGURE 3-14: TX Register Block Diagram (Before Transmit)66FIGURE 3-15: TX Register Block Diagram (During Transmit)67TABLE 3-3: Transmit Pin Function vs. Operation Mode68FIGURE 3-16: TX Register Usage69FIGURE 3-17: Multiple Byte Write with Transmit Register693.18 RX FIFO Buffered Data Read70FIGURE 3-18: Receiver FIFO Read703.18.1 Interrupt Mode713.18.2 Polling Mode71TABLE 3-4: Receive Pin Function vs. Operation Mode71FIGURE 3-19: FIFO Read Example with FINT Polling713.19 RX-TX Frequency Alignment Method724.0 Application Details73FIGURE 4-1: Application Circuit734.1 Antenna/Balun73FIGURE 4-2: Balun Circuit734.2 Antenna Design Considerations744.3 RF Transmitter Matching74TABLE 4-1: Frequency Band – Antenna Admittance/Impedance744.4 General PCB Layout Design74FIGURE 4-3: Two Basic Copper FR4 Layers74FIGURE 4-4: Four Basic Copper FR4 Layers744.5 MRF49XA Schematic and Bill of Materials764.5.1 Schematic76FIGURE 4-5: MRF49XA Schematic764.5.2 Bill of Materials77TABLE 4-2: MRF49XA: 433 MHz Bill of Materials77TABLE 4-3: MRF49XA: 868/915 MHz Bill of Materials785.0 Electrical Characteristics79Absolute Maximum Ratings(†)79TABLE 5-1: Recommended Operating Conditions80TABLE 5-2: Current Consumption(1)80TABLE 5-3: I/O Pin Input Specifications(1)80TABLE 5-4: Receiver AC Characteristics(1)81TABLE 5-5: Transmitter AC Characteristics(1)82TABLE 5-6: PLL Parameters AC Characteristics(1)82TABLE 5-7: Other Timing Parameters AC Characteristics(1)835.1 Timing Specification and Diagram84TABLE 5-8: SPI Timing Specification84FIGURE 5-1: SPI Timing Diagram845.2 Typical Performance Characteristics85FIGURE 5-2: Channel Selectivity and Blocking(1,2)85FIGURE 5-3: BER Curves in 433 MHz Band86FIGURE 5-4: BER Curves in 868 MHz Band86TABLE 5-9: RX BW and TX Deviation Frequency for Different Baud Rates87FIGURE 5-5: Receiver Sensitivity Over Ambient Temperature (433 MHz, 2.4 kbps, Dffsk: 45 kHz, BW: 67 kHz)88FIGURE 5-6: Receiver Sensitivity Over Ambient Temperature (868 MHz, 2.4 kbps, Dffsk: 45 kHz, BW: 67 kHz)886.0 Packaging Information896.1 Package Marking Information896.2 Package Details90Appendix A: Read Sequence and Packet Structures93FIGURE A-1: STSREG Read Sequence93TABLE A-1: Recommended FIFO Packet Structures93Appendix B: Revision History95Revision A (March 2009)95Revision B (June 2009)95Revision C (November 2011)95INDEX97The Microchip Web Site99Customer Change Notification Service99Customer Support99Reader Response100Product Identification System101Dimensioni: 1,76 MBPagine: 102Language: EnglishApri il manuale