Microchip Technology RF TXRX 433/868/915 TSSOP -16 MRF49XA-I/ST User Manuals

Table of Contents

• Features

  3
• RF/Analog Features

  3
• Baseband Features

  3
• Typical Applications

  3
• Pin Diagram: 16-Pin TSSOP

  4
• Table of Contents

  5
• Most Current Data Sheet

  5
• Errata

  5
• Customer Notification System

  5
• 1.0 Introduction

  7
  • FIGURE 1-1: Functional Node Block Diagram

    8
  • FIGURE 1-2: Microcontroller to MRF49XA Interface

    8
• 2.0 Hardware Description

  9
  • FIGURE 2-1: MRF49XA Architectural Block Diagram

    10
  • TABLE 2-1: Pin Description (Continued)

    11
  • 2.1 Power and Ground Pins

    13
    • TABLE 2-2: Recommended Bypass Capacitors Value

      13
    • TABLE 2-3: Recommended Bypass Capacitors

      13
  • 2.2 RESET Pin

    13
  • 2.3 Power Amplifier

    13
  • 2.4 Low Noise Amplifier

    13
  • 2.5 RFXTL/EXTREF and CLKOUT Pins

    14
  • 2.6 Phase-Locked Loop

    14
  • 2.7 Automatic Frequency Control

    14
  • 2.8 Baseband/Data Filters

    14
  • 2.9 Clock Recovery Circuit

    14
  • 2.10 Data Validity Blocks

    15
    • 2.10.1 Receive Signal Strength Indicator

      15
    • 2.10.2 Data Quality Indicator

      15
    • 2.10.3 Data Indicator Output

      15
      • FIGURE 2-2: Analog RSSI Voltage vs. RF Input Power

        15
  • 2.11 Power-Saving Blocks

    16
    • 2.11.1 Low Battery Voltage Detector

      16
    • 2.11.2 Wake-up Timer

      16
    • 2.11.3 Low Duty Cycle mode

      16
  • 2.12 INT, IRO Pins and Interrupts

    16
  • 2.13 Transmit Register

    16
  • 2.14 Receive FIFO

    17
  • 2.15 Serial Peripheral Interface

    17
  • 2.16 Memory Organization

    18
    • TABLE 2-4: Control (Command) Register Description

      18
  • 2.17 Control (Command) Register Details

    19
    • Register 2-1: STSREG: Status Read Register (POR: 0x0000)(1) (Continued)

      19
    • Register 2-2: GENCREG: General Configuration Register (POR: 0x8008)

      21
    • Register 2-3: AFCCREG: Automatic Frequency Control Configuration Register (POR: 0xC4F7)

      22
    • Register 2-4: TXCREG: Transmit Configuration Register (POR: 0x9800) (Continued)

      23
    • EQUATION 2-1:

      24
    • Register 2-5: TXBREG: Transmit Byte Register (POR: 0xB8AA)

      25
    • Register 2-6: CFSREG: Center Frequency Value Set Register (POR: 0xA680)

      26
    • EQUATION 2-2:

      26
    • TABLE 2-5: Center Frequency Value

      26
    • TABLE 2-6: Frequency Band Tuning Resolution

      26
    • Register 2-7: RXCREG: Receive Control Register (POR: 0x9080) (Continued)

      27
    • Register 2-8: BBFCREG: Baseband Filter Configuration Register (POR: 0xC22C)

      29
    • EQUATION 2-3:

      30
    • TABLE 2-7: Data Rate vs. Filter Capacitor Value

      30
    • Register 2-9: RXFIFOREG: Receiver FIFO Read Register (POR: 0xB000)

      31
    • Register 2-10: FIFORSTREG: FIFO and Reset Mode Configuration Register (POR: 0xCA80)

      32
    • TABLE 2-8: Synchronous Character Selection

      33
    • TABLE 2-9: Reset Mode Selection

      33
    • Register 2-11: SYNBREG: Synchronous Byte Configuration Register (POR: 0xCED4)

      34
    • Register 2-12: DRSREG: Data Rate Value Set Register (POR: 0xC623)

      35
    • EQUATION 2-4:

      35
    • EQUATION 2-5:

      35
    • EQUATION 2-6:

      35
    • Register 2-13: PMCREG: Power Management Configuration Register (POR: 0x8208) (Continued)

      36
    • Register 2-14: WTSREG: Wake-up Timer Value Set Register (POR: 0xE196)

      38
    • EQUATION 2-7:

      38
    • Register 2-15: DCSREG: Duty Cycle Value Set Register (POR: 0xC80E)

      39
    • EQUATION 2-8:

      39
    • Register 2-16: BCSREG: Battery Threshold Detect and Clock Output Value Set Register (POR: 0xC000)

      40
    • EQUATION 2-9:

      40
    • Register 2-17: PLLCREG: PLL Configuration Register (POR: 0xCC77)

      41
    • TABLE 2-10: Control/Command Register Map

      42
• 3.0 Functional Description

  43
  • 3.1 Reset

    43
    • 3.1.1 Power-on Reset

      43
      • FIGURE 3-1: Power-on Reset Example

        43
    • 3.1.2 Power Glitch Reset

      44
      • FIGURE 3-2: Sensitive Reset Enabled

        44
      • FIGURE 3-3: Sensitive Reset Disabled

        45
    • 3.1.3 Software Reset

      45
    • 3.1.4 Reset Pin

      45
      • FIGURE 3-4: RESET Pin Internal Connection

        45
  • 3.2 Vdd Line Filtering

    46
  • 3.3 Power and Low Noise Amplifiers

    47
  • 3.4 Crystal Oscillator and Clock Output

    47
    • TABLE 3-1: Programmable Load Capacitance Value

      47
    • 3.4.1 Clock Tail Feature

      47
    • 3.4.2 Auto Crystal Oscillator

      48
  • 3.5 Phase-Locked Loop

    48
  • 3.6 Crystal Selection Guidelines

    49
    • FIGURE 3-5: Maximum Crystal Tolerances Including Temperature and Aging (ppm)

      49
  • 3.7 Automatic Frequency Control

    50
    • FIGURE 3-6: AFC Circuit for Frequency Offset Correction

      51
  • 3.8 Initialization

    52
  • 3.9 Interrupts

    52
    • 3.9.1 Setting Interrupts

      53
    • 3.9.2 Clearing Interrupts

      53
      • FIGURE 3-7: MRF49XA Interrupt Generation Logic

        55
  • 3.10 Baseband/Data Filtering

    56
    • FIGURE 3-8: Full Baseband Amplifier Transfer Function (BW = 67 kHz)

      56
    • EXAMPLE 3-1: Frequency Deviation and BBBW Calculation

      56
    • FIGURE 3-9: FSK Modulated Deviation – Maximum TX TO RX Offset

      57
    • 3.10.1 Analog Filtering Mode

      57
    • 3.10.2 Digital Filtering Mode

      57
  • 3.11 Data Quality Indicator

    58
    • EQUATION 3-1:

      58
    • FIGURE 3-10: DIO Logic Block Diagram

      58
  • 3.12 Programmable Synchronous Byte

    59
  • 3.13 Received Signal Strength Indicator

    59
    • EQUATION 3-2:

      59
    • TABLE 3-2: Digital RSSI Threshold Levels

      60
    • FIGURE 3-11: Input Power vs. Analog RSSI Voltage

      60
    • 3.13.1 Relationship Between RSSI and Clock Recovery

      60
    • 3.13.2 Relationship Between RSSI and AFC

      60
  • 3.14 Power Management

    61
    • FIGURE 3-12: Logic Connections Between Power Control Bits

      63
  • 3.15 Low Duty Cycle Mode

    64
    • EQUATION 3-3:

      64
    • FIGURE 3-13: Low-Power Duty Cycle Mode Sequence

      64
  • 3.16 Sleep, Wake-up and Battery Operations

    65
    • EQUATION 3-4:

      65
    • EQUATION 3-5:

      65
  • 3.17 TX Register Buffered Data Transmission

    66
    • EQUATION 3-6:

      66
    • FIGURE 3-14: TX Register Block Diagram (Before Transmit)

      66
    • FIGURE 3-15: TX Register Block Diagram (During Transmit)

      67
    • TABLE 3-3: Transmit Pin Function vs. Operation Mode

      68
    • FIGURE 3-16: TX Register Usage

      69
    • FIGURE 3-17: Multiple Byte Write with Transmit Register

      69
  • 3.18 RX FIFO Buffered Data Read

    70
    • FIGURE 3-18: Receiver FIFO Read

      70
    • 3.18.1 Interrupt Mode

      71
    • 3.18.2 Polling Mode

      71
      • TABLE 3-4: Receive Pin Function vs. Operation Mode

        71
      • FIGURE 3-19: FIFO Read Example with FINT Polling

        71
  • 3.19 RX-TX Frequency Alignment Method

    72
• 4.0 Application Details

  73
  • FIGURE 4-1: Application Circuit

    73
  • 4.1 Antenna/Balun

    73
    • FIGURE 4-2: Balun Circuit

      73
  • 4.2 Antenna Design Considerations

    74
  • 4.3 RF Transmitter Matching

    74
    • TABLE 4-1: Frequency Band – Antenna Admittance/Impedance

      74
  • 4.4 General PCB Layout Design

    74
    • FIGURE 4-3: Two Basic Copper FR4 Layers

      74
    • FIGURE 4-4: Four Basic Copper FR4 Layers

      74
  • 4.5 MRF49XA Schematic and Bill of Materials

    76
    • 4.5.1 Schematic

      76
      • FIGURE 4-5: MRF49XA Schematic

        76
    • 4.5.2 Bill of Materials

      77
      • TABLE 4-2: MRF49XA: 433 MHz Bill of Materials

        77
      • TABLE 4-3: MRF49XA: 868/915 MHz Bill of Materials

        78
• 5.0 Electrical Characteristics

  79
  • Absolute Maximum Ratings(†)

    79
    • TABLE 5-1: Recommended Operating Conditions

      80
    • TABLE 5-2: Current Consumption(1)

      80
    • TABLE 5-3: I/O Pin Input Specifications(1)

      80
    • TABLE 5-4: Receiver AC Characteristics(1)

      81
    • TABLE 5-5: Transmitter AC Characteristics(1)

      82
    • TABLE 5-6: PLL Parameters AC Characteristics(1)

      82
    • TABLE 5-7: Other Timing Parameters AC Characteristics(1)

      83
  • 5.1 Timing Specification and Diagram

    84
    • TABLE 5-8: SPI Timing Specification

      84
    • FIGURE 5-1: SPI Timing Diagram

      84
  • 5.2 Typical Performance Characteristics

    85
    • FIGURE 5-2: Channel Selectivity and Blocking(1,2)

      85
    • FIGURE 5-3: BER Curves in 433 MHz Band

      86
    • FIGURE 5-4: BER Curves in 868 MHz Band

      86
    • TABLE 5-9: RX BW and TX Deviation Frequency for Different Baud Rates

      87
    • FIGURE 5-5: Receiver Sensitivity Over Ambient Temperature (433 MHz, 2.4 kbps, Dffsk: 45 kHz, BW: 67 kHz)

      88
    • FIGURE 5-6: Receiver Sensitivity Over Ambient Temperature (868 MHz, 2.4 kbps, Dffsk: 45 kHz, BW: 67 kHz)

      88
• 6.0 Packaging Information

  89
  • 6.1 Package Marking Information

    89
  • 6.2 Package Details

    90
• Appendix A: Read Sequence and Packet Structures

  93
  • FIGURE A-1: STSREG Read Sequence

    93
  • TABLE A-1: Recommended FIFO Packet Structures

    93
• Appendix B: Revision History

  95
  • Revision A (March 2009)

    95
  • Revision B (June 2009)

    95
  • Revision C (November 2011)

    95
  • INDEX

    97
• The Microchip Web Site

  99
• Customer Change Notification Service

  99
• Customer Support

  99
• Reader Response

  100
• Product Identification System

  101