用户手册 — Microchip Technology RF TXRX 433/868/915 TSSOP -16 MRF49XA-I/ST

目录

• Features

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• RF/Analog Features

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• Baseband Features

  3
• Typical Applications

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• Pin Diagram: 16-Pin TSSOP

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• Table of Contents

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• Most Current Data Sheet

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• Errata

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• Customer Notification System

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• 1.0 Introduction

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  • FIGURE 1-1: Functional Node Block Diagram

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  • FIGURE 1-2: Microcontroller to MRF49XA Interface

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• 2.0 Hardware Description

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  • FIGURE 2-1: MRF49XA Architectural Block Diagram

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  • TABLE 2-1: Pin Description (Continued)

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  • 2.1 Power and Ground Pins

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    • TABLE 2-2: Recommended Bypass Capacitors Value

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    • TABLE 2-3: Recommended Bypass Capacitors

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  • 2.2 RESET Pin

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  • 2.3 Power Amplifier

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  • 2.4 Low Noise Amplifier

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  • 2.5 RFXTL/EXTREF and CLKOUT Pins

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  • 2.6 Phase-Locked Loop

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  • 2.7 Automatic Frequency Control

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  • 2.8 Baseband/Data Filters

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  • 2.9 Clock Recovery Circuit

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  • 2.10 Data Validity Blocks

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    • 2.10.1 Receive Signal Strength Indicator

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    • 2.10.2 Data Quality Indicator

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    • 2.10.3 Data Indicator Output

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      • FIGURE 2-2: Analog RSSI Voltage vs. RF Input Power

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  • 2.11 Power-Saving Blocks

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    • 2.11.1 Low Battery Voltage Detector

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    • 2.11.2 Wake-up Timer

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    • 2.11.3 Low Duty Cycle mode

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  • 2.12 INT, IRO Pins and Interrupts

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  • 2.13 Transmit Register

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  • 2.14 Receive FIFO

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  • 2.15 Serial Peripheral Interface

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  • 2.16 Memory Organization

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    • TABLE 2-4: Control (Command) Register Description

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  • 2.17 Control (Command) Register Details

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    • Register 2-1: STSREG: Status Read Register (POR: 0x0000)(1) (Continued)

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    • Register 2-2: GENCREG: General Configuration Register (POR: 0x8008)

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    • Register 2-3: AFCCREG: Automatic Frequency Control Configuration Register (POR: 0xC4F7)

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    • Register 2-4: TXCREG: Transmit Configuration Register (POR: 0x9800) (Continued)

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    • EQUATION 2-1:

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    • Register 2-5: TXBREG: Transmit Byte Register (POR: 0xB8AA)

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    • Register 2-6: CFSREG: Center Frequency Value Set Register (POR: 0xA680)

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    • EQUATION 2-2:

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    • TABLE 2-5: Center Frequency Value

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    • TABLE 2-6: Frequency Band Tuning Resolution

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    • Register 2-7: RXCREG: Receive Control Register (POR: 0x9080) (Continued)

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    • Register 2-8: BBFCREG: Baseband Filter Configuration Register (POR: 0xC22C)

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    • EQUATION 2-3:

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    • TABLE 2-7: Data Rate vs. Filter Capacitor Value

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    • Register 2-9: RXFIFOREG: Receiver FIFO Read Register (POR: 0xB000)

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    • Register 2-10: FIFORSTREG: FIFO and Reset Mode Configuration Register (POR: 0xCA80)

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    • TABLE 2-8: Synchronous Character Selection

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    • TABLE 2-9: Reset Mode Selection

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    • Register 2-11: SYNBREG: Synchronous Byte Configuration Register (POR: 0xCED4)

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    • Register 2-12: DRSREG: Data Rate Value Set Register (POR: 0xC623)

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    • EQUATION 2-4:

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    • EQUATION 2-5:

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    • EQUATION 2-6:

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    • Register 2-13: PMCREG: Power Management Configuration Register (POR: 0x8208) (Continued)

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    • Register 2-14: WTSREG: Wake-up Timer Value Set Register (POR: 0xE196)

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    • EQUATION 2-7:

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    • Register 2-15: DCSREG: Duty Cycle Value Set Register (POR: 0xC80E)

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    • EQUATION 2-8:

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    • Register 2-16: BCSREG: Battery Threshold Detect and Clock Output Value Set Register (POR: 0xC000)

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    • EQUATION 2-9:

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    • Register 2-17: PLLCREG: PLL Configuration Register (POR: 0xCC77)

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    • TABLE 2-10: Control/Command Register Map

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• 3.0 Functional Description

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  • 3.1 Reset

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    • 3.1.1 Power-on Reset

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      • FIGURE 3-1: Power-on Reset Example

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    • 3.1.2 Power Glitch Reset

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      • FIGURE 3-2: Sensitive Reset Enabled

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      • FIGURE 3-3: Sensitive Reset Disabled

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    • 3.1.3 Software Reset

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    • 3.1.4 Reset Pin

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      • FIGURE 3-4: RESET Pin Internal Connection

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  • 3.2 Vdd Line Filtering

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  • 3.3 Power and Low Noise Amplifiers

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  • 3.4 Crystal Oscillator and Clock Output

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    • TABLE 3-1: Programmable Load Capacitance Value

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    • 3.4.1 Clock Tail Feature

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    • 3.4.2 Auto Crystal Oscillator

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  • 3.5 Phase-Locked Loop

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  • 3.6 Crystal Selection Guidelines

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    • FIGURE 3-5: Maximum Crystal Tolerances Including Temperature and Aging (ppm)

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  • 3.7 Automatic Frequency Control

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    • FIGURE 3-6: AFC Circuit for Frequency Offset Correction

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  • 3.8 Initialization

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  • 3.9 Interrupts

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    • 3.9.1 Setting Interrupts

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    • 3.9.2 Clearing Interrupts

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      • FIGURE 3-7: MRF49XA Interrupt Generation Logic

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  • 3.10 Baseband/Data Filtering

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    • FIGURE 3-8: Full Baseband Amplifier Transfer Function (BW = 67 kHz)

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    • EXAMPLE 3-1: Frequency Deviation and BBBW Calculation

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    • FIGURE 3-9: FSK Modulated Deviation – Maximum TX TO RX Offset

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    • 3.10.1 Analog Filtering Mode

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    • 3.10.2 Digital Filtering Mode

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  • 3.11 Data Quality Indicator

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    • EQUATION 3-1:

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    • FIGURE 3-10: DIO Logic Block Diagram

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  • 3.12 Programmable Synchronous Byte

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  • 3.13 Received Signal Strength Indicator

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    • EQUATION 3-2:

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    • TABLE 3-2: Digital RSSI Threshold Levels

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    • FIGURE 3-11: Input Power vs. Analog RSSI Voltage

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    • 3.13.1 Relationship Between RSSI and Clock Recovery

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    • 3.13.2 Relationship Between RSSI and AFC

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  • 3.14 Power Management

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    • FIGURE 3-12: Logic Connections Between Power Control Bits

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  • 3.15 Low Duty Cycle Mode

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    • EQUATION 3-3:

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    • FIGURE 3-13: Low-Power Duty Cycle Mode Sequence

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  • 3.16 Sleep, Wake-up and Battery Operations

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    • EQUATION 3-4:

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    • EQUATION 3-5:

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  • 3.17 TX Register Buffered Data Transmission

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    • EQUATION 3-6:

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    • FIGURE 3-14: TX Register Block Diagram (Before Transmit)

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    • FIGURE 3-15: TX Register Block Diagram (During Transmit)

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    • TABLE 3-3: Transmit Pin Function vs. Operation Mode

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    • FIGURE 3-16: TX Register Usage

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    • FIGURE 3-17: Multiple Byte Write with Transmit Register

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  • 3.18 RX FIFO Buffered Data Read

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    • FIGURE 3-18: Receiver FIFO Read

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    • 3.18.1 Interrupt Mode

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    • 3.18.2 Polling Mode

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      • TABLE 3-4: Receive Pin Function vs. Operation Mode

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      • FIGURE 3-19: FIFO Read Example with FINT Polling

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  • 3.19 RX-TX Frequency Alignment Method

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• 4.0 Application Details

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  • FIGURE 4-1: Application Circuit

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  • 4.1 Antenna/Balun

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    • FIGURE 4-2: Balun Circuit

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  • 4.2 Antenna Design Considerations

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  • 4.3 RF Transmitter Matching

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    • TABLE 4-1: Frequency Band – Antenna Admittance/Impedance

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  • 4.4 General PCB Layout Design

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    • FIGURE 4-3: Two Basic Copper FR4 Layers

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    • FIGURE 4-4: Four Basic Copper FR4 Layers

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  • 4.5 MRF49XA Schematic and Bill of Materials

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    • 4.5.1 Schematic

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      • FIGURE 4-5: MRF49XA Schematic

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    • 4.5.2 Bill of Materials

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      • TABLE 4-2: MRF49XA: 433 MHz Bill of Materials

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      • TABLE 4-3: MRF49XA: 868/915 MHz Bill of Materials

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• 5.0 Electrical Characteristics

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  • Absolute Maximum Ratings(†)

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    • TABLE 5-1: Recommended Operating Conditions

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    • TABLE 5-2: Current Consumption(1)

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    • TABLE 5-3: I/O Pin Input Specifications(1)

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    • TABLE 5-4: Receiver AC Characteristics(1)

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    • TABLE 5-5: Transmitter AC Characteristics(1)

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    • TABLE 5-6: PLL Parameters AC Characteristics(1)

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    • TABLE 5-7: Other Timing Parameters AC Characteristics(1)

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  • 5.1 Timing Specification and Diagram

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    • TABLE 5-8: SPI Timing Specification

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    • FIGURE 5-1: SPI Timing Diagram

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  • 5.2 Typical Performance Characteristics

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    • FIGURE 5-2: Channel Selectivity and Blocking(1,2)

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    • FIGURE 5-3: BER Curves in 433 MHz Band

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    • FIGURE 5-4: BER Curves in 868 MHz Band

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    • TABLE 5-9: RX BW and TX Deviation Frequency for Different Baud Rates

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    • FIGURE 5-5: Receiver Sensitivity Over Ambient Temperature (433 MHz, 2.4 kbps, Dffsk: 45 kHz, BW: 67 kHz)

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    • FIGURE 5-6: Receiver Sensitivity Over Ambient Temperature (868 MHz, 2.4 kbps, Dffsk: 45 kHz, BW: 67 kHz)

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• 6.0 Packaging Information

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  • 6.1 Package Marking Information

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  • 6.2 Package Details

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• Appendix A: Read Sequence and Packet Structures

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  • FIGURE A-1: STSREG Read Sequence

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  • TABLE A-1: Recommended FIFO Packet Structures

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• Appendix B: Revision History

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  • Revision A (March 2009)

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  • Revision B (June 2009)

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  • Revision C (November 2011)

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  • INDEX

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• The Microchip Web Site

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• Customer Change Notification Service

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• Customer Support

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• Reader Response

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• Product Identification System

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