Motorola DSP56301 ユーザーズマニュアル
Operation
Enhanced Synchronous Serial Interface (ESSI)
7
-7
ESSI, use an ESSI individual reset when you change the ESSI control registers (except for
bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE).
bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE).
Here is an example of how to initialize the ESSI.
1.
Put the ESSI in its individual reset state by clearing the PCR bits.
2.
Configure the control registers (CRA, CRB) to set the operating mode. Disable the
transmitters and receiver by clearing the TE[2–0] and RE bits. Set the interrupt enable
bits for the operating mode chosen.
transmitters and receiver by clearing the TE[2–0] and RE bits. Set the interrupt enable
bits for the operating mode chosen.
3.
Enable the ESSI by setting the PCR bits to activate the input/output signals to be used.
4.
Write initial data to the transmitters that are in use during operation. This step is
needed even if DMA services the transmitters.
needed even if DMA services the transmitters.
5.
Enable the transmitters and receiver to be used.
Now the ESSI can be serviced by polling, interrupts, or DMA. Once the ESSI is enabled (Step
3), operation starts as follows:
3), operation starts as follows:
1.
For internally generated clock and frame sync, these signals start activity immediately
after the ESSI is enabled.
after the ESSI is enabled.
2.
The ESSI receives data after a frame sync signal (either internally or externally gener-
ated) only when the receive enable (RE) bit is set.
ated) only when the receive enable (RE) bit is set.
3.
Data is transmitted after a frame sync signal (either internally or externally generated)
only when the transmitter enable (TE[2–0]) bit is set.
only when the transmitter enable (TE[2–0]) bit is set.
7.3.3
Exceptions
The ESSI can generate six different exceptions. They are discussed in the following
paragraphs (ordered from the highest to the lowest exception priority):
paragraphs (ordered from the highest to the lowest exception priority):
n
ESSI receive data with exception status:
Occurs when the receive exception interrupt is enabled, the receive data register is full,
and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE
bit is cleared when you first read the SSISR and then read the Receive Data Register
(RX).
Occurs when the receive exception interrupt is enabled, the receive data register is full,
and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE
bit is cleared when you first read the SSISR and then read the Receive Data Register
(RX).
n
ESSI receive data:
Occurs when the receive interrupt is enabled, the receive data register is full, and no
receive error conditions exist. A read of RX clears the pending interrupt. This
error-free interrupt can use a fast interrupt service routine for minimum overhead.
Occurs when the receive interrupt is enabled, the receive data register is full, and no
receive error conditions exist. A read of RX clears the pending interrupt. This
error-free interrupt can use a fast interrupt service routine for minimum overhead.