Motorola DSP56301 ユーザーズマニュアル
Operation
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DSP56301 User’s Manual
n
ESSI receive last slot interrupt:
Occurs when the ESSI is in Network mode and the last slot of the frame has ended.
This interrupt is generated regardless of the receive mask register setting. The receive
last slot interrupt can signal that the receive mask slot register can be reset, the DMA
channels can be reconfigured, and data memory pointers can be reassigned. Using the
receive last slot interrupt guarantees that the previous frame is serviced with the
previous setting and the new frame is serviced with the new setting without
synchronization problems.
Occurs when the ESSI is in Network mode and the last slot of the frame has ended.
This interrupt is generated regardless of the receive mask register setting. The receive
last slot interrupt can signal that the receive mask slot register can be reset, the DMA
channels can be reconfigured, and data memory pointers can be reassigned. Using the
receive last slot interrupt guarantees that the previous frame is serviced with the
previous setting and the new frame is serviced with the new setting without
synchronization problems.
Note:
The maximum time it takes to service a receive last slot interrupt should not exceed
N – 1 ESSI bits service time (where N is the number of bits the ESSI can transmit
per time slot).
N – 1 ESSI bits service time (where N is the number of bits the ESSI can transmit
per time slot).
n
ESSI transmit data with exception status:
Occurs when the transmit exception interrupt is enabled, at least one transmit data
register of the enabled transmitters is empty, and a transmitter underrun error has
occurred. This exception sets the SSISR[TUE] bit. The TUE bit is cleared when you
first read the SSISR and then write to all the transmit data registers of the enabled
transmitters, or when you write to TSR to clear the pending interrupt.
Occurs when the transmit exception interrupt is enabled, at least one transmit data
register of the enabled transmitters is empty, and a transmitter underrun error has
occurred. This exception sets the SSISR[TUE] bit. The TUE bit is cleared when you
first read the SSISR and then write to all the transmit data registers of the enabled
transmitters, or when you write to TSR to clear the pending interrupt.
n
ESSI transmit last slot interrupt:
Occurs when the ESSI is in Network mode at the start of the last slot of the frame. This
exception occurs regardless of the transmit mask register setting. The transmit last slot
interrupt can signal that the transmit mask slot register can be reset, the DMA channels
can be reconfigured, and data memory pointers can be reassigned. Using the Transmit
Last Slot interrupt guarantees that the previous frame is serviced with the previous
frame settings and the new frame is serviced with the new frame settings without
synchronization problems.
Occurs when the ESSI is in Network mode at the start of the last slot of the frame. This
exception occurs regardless of the transmit mask register setting. The transmit last slot
interrupt can signal that the transmit mask slot register can be reset, the DMA channels
can be reconfigured, and data memory pointers can be reassigned. Using the Transmit
Last Slot interrupt guarantees that the previous frame is serviced with the previous
frame settings and the new frame is serviced with the new frame settings without
synchronization problems.
Note:
The maximum transmit last slot interrupt service time should not exceed
N – 1 ESSI bits service time (where N is the number of bits in a slot).
N – 1 ESSI bits service time (where N is the number of bits in a slot).
n
ESSI transmit data:
Occurs when the transmit interrupt is enabled, at least one of the enabled transmit data
registers is empty, and no transmitter error conditions exist. Write to all the enabled
TX registers or to the TSR to clear this interrupt. This error-free interrupt uses a fast
interrupt service routine for minimum overhead (if no more than two transmitters are
used).
Occurs when the transmit interrupt is enabled, at least one of the enabled transmit data
registers is empty, and no transmitter error conditions exist. Write to all the enabled
TX registers or to the TSR to clear this interrupt. This error-free interrupt uses a fast
interrupt service routine for minimum overhead (if no more than two transmitters are
used).