Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

When the Watchdog counter underflows, the program counter will start from 0x0000 0000 
as in the case of external reset. The Watchdog time-out flag (WDTOF) can be examined 
to determine if the Watchdog has caused the reset condition. The WDTOF flag must be 
cleared by software.

The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB 
accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting.

There is some synchronization logic between these two clock domains. When the 
WDMOD and WDTC registers are updated by APB operations, the new value will take 
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog 
timer is counting on WDCLK, the synchronization logic will first lock the value of the 
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV 
register by the CPU.

The Watchdog contains 4 registers as shown in 

 below.

 

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

The WDMOD register controls the operation of the Watchdog as per the combination of 
WDEN and RESET bits.

WDMOD

Watchdog mode register. This register contains 
the basic mode and status of the Watchdog 
Timer.

R/W

0

0xE000 0000

WDTC

Watchdog timer constant register. This register 
determines the time-out value.

R/W

0xFF

0xE000 0004

WDFEED

Watchdog feed sequence register. Writing 0xAA 
followed by 0x55 to this register reloads the 
Watchdog timer with the value contained in 
WDTC.

WO

NA

0xE000 0008

WDTV

Watchdog timer value register. This register 
reads out the current value of the Watchdog 
timer.

RO

0xFF

0xE000 000C

WDCLKSEL Watchdog clock source selection register.

R/W

0

0xE000 0010