Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
665 of 792
NXP Semiconductors
UM10237
Chapter 27: LPC24XX WatchDog Timer (WDT)
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.
interrupt happens during the feed sequence.
4.4 Watchdog Timer Value Register (WDTV - 0xE000 000C)
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 32 bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
4.5 Watchdog Timer Clock Source Selection Register (WDCLKSEL -
0xE000 0010)
This register allows selecting the clock source for the Watchdog timer. The possibilities are: the
Internal RC oscillator (IRC), the RTC oscillator, and the APB peripheral clock (pclk). The function of
bits in WDCLKSEL are shown in
bits in WDCLKSEL are shown in
Table 589: Watchdog Feed Register (WDFEED - address 0xE000 0008) bit description
Bit
Symbol
Description
Reset Value
7:0
Feed
Feed value should be 0xAA followed by 0x55.
NA
Table 590: Watchdog Timer Value register (WDTV - address 0xE000 000C) bit description
Bit
Symbol
Description
Reset Value
31:0
Count
Counter timer value.
0x0000 00FF
Table 591: Watchdog Timer Clock Source Selection register (WDCLKSEL - address
0xE000 0010) bit description
Bit
Symbol Value Description
Reset
Value
Value
1:0
WDSEL
These bits select the clock source for the Watchdog timer as
described below.
described below.
Warning:
Improper setting of this value may result in incorrect
operation of the Watchdog timer, which could adversely affect
system operation.
system operation.
0
00
Selects the Internal RC oscillator as the Watchdog clock source
(default).
(default).
01
Selects the APB peripheral clock (PCLK) as the Watchdog clock
source.
source.
10
Selects the RTC oscillator as the Watchdog clock source.
11
Reserved
31:2 -
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA