Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
664 of 792
NXP Semiconductors
UM10237
Chapter 27: LPC24XX WatchDog Timer (WDT)
Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both
flags are cleared by an external reset or a Watchdog timer underflow.
flags are cleared by an external reset or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is
cleared by software.
cleared by software.
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the VIC or the watchdog interrupt request will be generated indefinitely.
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the VIC or the watchdog interrupt request will be generated indefinitely.
4.2 Watchdog Timer Constant Register (WDTC - 0xE000 0004)
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. It’s a 32 bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is T
the WDTC content is reloaded in to the Watchdog timer. It’s a 32 bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is T
WDCLK
× 256 × 4.
4.3 Watchdog Feed Register (WDFEED - 0xE000 0008)
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
Table 586. Watchdog operating modes selection
WDEN
WDRESET
Mode of Operation
0
X (0 or 1)
Debug/Operate without the Watchdog running.
1
0
Watchdog interrupt mode: debug with the Watchdog interrupt but no
WDRESET enabled.
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will set the
WDINT flag and the Watchdog interrupt request will be generated.
WDINT flag and the Watchdog interrupt request will be generated.
1
1
Watchdog reset mode: operate with the Watchdog interrupt and
WDRESET enabled.
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will reset
the microcontroller. Although the Watchdog interrupt is also enabled in
this case (WDEN = 1) it will not be recognized since the watchdog
reset will clear the WDINT flag.
the microcontroller. Although the Watchdog interrupt is also enabled in
this case (WDEN = 1) it will not be recognized since the watchdog
reset will clear the WDINT flag.
Table 587: Watchdog Mode register (WDMOD - address 0xE000 0000) bit description
Bit
Symbol
Description
Reset Value
0
WDEN
WDEN Watchdog interrupt enable bit (Set Only).
0
1
WDRESET WDRESET Watchdog reset enable bit (Set Only).
0
2
WDTOF
WDTOF Watchdog time-out flag.
0 (Only after
external reset)
external reset)
3
WDINT
WDINT Watchdog interrupt flag (Read Only).
0
7:4
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA
Table 588: Watchdog Constant register (WDTC - address 0xE000 0004) bit description
Bit
Symbol
Description
Reset Value
31:0
Count
Watchdog time-out interval.
0x0000 00FF