Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
111
The Quadrature Decoder generates an interrupt when the counter increments from 0xFF to
0x00 or when the counter decrements from 0x00 to 0xFF. The timing for the interrupt is
shown below. Note that the status bits in the QDCSR are set coincident with the interrupt,
and the interrupt (and status bits) are cleared by reading the QDCSR.
0x00 or when the counter decrements from 0x00 to 0xFF. The timing for the interrupt is
shown below. Note that the status bits in the QDCSR are set coincident with the interrupt,
and the interrupt (and status bits) are cleared by reading the QDCSR.
Rejected
Accepted
Peri Clock
Timer A10