Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
119
8.4 Memory Interface Unit
The 20-bit memory addresses generated by the memory-mapping unit feed into the mem-
ory interface unit. The memory interface unit has a separate write-only control register for
each 256K quadrant of the 1M physical memory. This control register specifies how mem-
ory access requests to that quadrant are to be dispatched to the memory chips connected to
the Rabbit. There are three separate chip select output lines (/CS0, /CS1, and /CS2) that
can be used to select one of three different memory chips. A field in the control register
determines which chip select is selected for memory accesses to the quadrant. The same
chip select line may be accessed in more than one quadrant. For example, if a 512K RAM
is installed and is selected by /CS1, it would be appropriate to use /CS1 for accesses to the
3rd and 4th quadrants, thus mapping the RAM chip to addresses 0x80000 to 0x0FFFFF.
ory interface unit. The memory interface unit has a separate write-only control register for
each 256K quadrant of the 1M physical memory. This control register specifies how mem-
ory access requests to that quadrant are to be dispatched to the memory chips connected to
the Rabbit. There are three separate chip select output lines (/CS0, /CS1, and /CS2) that
can be used to select one of three different memory chips. A field in the control register
determines which chip select is selected for memory accesses to the quadrant. The same
chip select line may be accessed in more than one quadrant. For example, if a 512K RAM
is installed and is selected by /CS1, it would be appropriate to use /CS1 for accesses to the
3rd and 4th quadrants, thus mapping the RAM chip to addresses 0x80000 to 0x0FFFFF.