Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
121
Bit 3—Inhibits the write pulse to memory accessed in this quadrant. Useful for protecting flash mem-
ory from an inadvertent write pulse, which will not actually write to the flash because it is protected
by lock codes, but will temporarily disable the flash memory and crash the system if the memory is
used for code.
by lock codes, but will temporarily disable the flash memory and crash the system if the memory is
used for code.
Bit 2—Selects which set of the two lines /OEx and /WEx will be driven for memory accesses in this
quadrant.
Bits 1,0—Determines which of the three chip select lines will be driven for memory accesses to this
quadrant.
All bits of the control register are initialized to zero on reset.
8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable)
The inversion of A19 or A16 controlled by the read/write MMIDR register is used to
redirect mapping of the root segment and the data segment by inverting certain bits when
these segments are accessed.
redirect mapping of the root segment and the data segment by inverting certain bits when
these segments are accessed.
The optional enable of /CS1 is valuable for systems that are pushing the access time of
battery-backed RAM. By enabling /CS1, the delay time of the switch that forces /CS1
high when power is off can be bypassed. This feature increases power consumption since
the RAM is always enabled and its access is controlled normally by /OE1.
battery-backed RAM. By enabling /CS1, the delay time of the switch that forces /CS1
high when power is off can be bypassed. This feature increases power consumption since
the RAM is always enabled and its access is controlled normally by /OE1.
Table 8-4. MMU Instruction/Data Register (MMIDR = 0x010)
*
* See Table B-20 for information on bit 7 for Rabbit 3000A and later versions.
MMU Instruction/Data Register
(MMIDR)
(Address = 0x010)
Bit(s)
Value
Description
7:6
00
These bits are ignored and always return zeros when read.
5
0
Enable A16 and A19 inversion independent of instruction/data.
1
Enable A16 and A19 inversion (controlled by bits 0–3) for data accesses only.
This enables the instruction/data split. This is separate I and D space.
This enables the instruction/data split. This is separate I and D space.
4
0
Normal /CS1 operation.
1
Force /CS1 always active. This will not cause any conflicts as long as the
memory using /CS1 does not also share an Output Enable or Write Enable with
another memory.
memory using /CS1 does not also share an Output Enable or Write Enable with
another memory.
3
0
Normal operation.
1
For a DATASEG access, invert A19 before MBxCR (bank select) decision.
2
0
Normal operation.
1
For a DATASEG access: invert A16
1
0
Normal operation.
1
For root access, invert A19 before MBxCR (bank select) decision.
0
0
Normal operation.
1
For root access, invert A16