Jameco Electronics 3000 ユーザーズマニュアル

The following registers are described in Table 9-17 and in Table 9-18.

PGDR—Port G data register. Reads value at pins. Writes to port G preload register.

PGCR—Parallel Port G control register. This register is used to control the clocking of 
the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, 
and 5 are reset to zero.

PGFR—Port G function register. Set bit to "1" to enable alternate output function. Bits 
6 and 2 enable the asycnhronous or SDLC/HDLC serial ports E and F outputs.  And 
bits 5-4 and 1-0 enable the SDLC/HDLC transmit and receive clock outputs for serial 
ports E and F.

PGDCR—Parallel Port G drive control register. A "0" makes the corresponding pin a 
regular output. A "1" makes the corresponding pin an open-drain output. Write only.

PGDDR—Port G data direction register. Set to "1" to make corresponding pin an out-
put. This register is zeroed on reset.

On reset, the data direction register is zeroed, making all pins inputs. In addition certain 
bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the 
output registers when loaded. All other registers associated with port G are not initialized 
on reset. 

x,x

00—clock upper nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

x,x

00—clock lower nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2