Jameco Electronics 3000 ユーザーズマニュアル
146
Rabbit 3000 Microprocessor
Table 10-1 shows how the eight I/O bank control registers are organized.
Table 10-1. I/O Bank x Control Register
I/O Bank x Control Register
(IB0CR)
(Address = 0x0080)
(IB1CR)
(Address = 0x0081)
(IB2CR)
(Address = 0x0082)
(IB3CR)
(Address = 0x0083)
(IB4CR)
(Address = 0x0084)
(IB5CR)
(Address = 0x0085)
(IB6CR)
(Address = 0x0086)
(IB7CR)
(Address = 0x0087)
Bit(s)
Value
Description
7:6
00
Fifteen wait states for accesses in this bank.
01
Seven wait states for accesses in this bank.
10
Three wait states for accesses in this bank.
11
One wait state for accesses in this bank.
5:4
00
The Ix signal is an I/O chip select.
01
The Ix signal is an I/O read strobe.
10
The Ix signal is an I/O write strobe.
11
The Ix signal is an I/O data (read or write) strobe.
3
0
Writes are not allowed to this bank. Transactions are normal in every other way;
only the write strobe is inhibited.
only the write strobe is inhibited.
1
Writes are allowed to this bank.
2
0
I/O strobe (Ix) is active low.
1
I/O strobe (Ix) is active high.
1:0
These bits are ignored.