Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
155
The time constant register for each timer (TATxR) is simply an 8-bit data register holding
a number between 0 and 255. This time constant will take effect the next time that the
Timer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n
is the programmed time constant. The time constant registers are write only. The time
constant registers are listed in Table 11-1.
a number between 0 and 255. This time constant will take effect the next time that the
Timer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n
is the programmed time constant. The time constant registers are write only. The time
constant registers are listed in Table 11-1.
11.1.2 Practical Use of Timer A
Timer A is disabled (bit 0 in control and status register) on power-up. Timer A is normally
set up while the clock is disabled, but the timer setup can be changed while the timer is
running when there is a need to do so. Timers that are not used should be driven from the
output of A1 and the reload register should be set to 255. This will cause counting to be as
slow as possible and consume minimum power.
set up while the clock is disabled, but the timer setup can be changed while the timer is
running when there is a need to do so. Timers that are not used should be driven from the
output of A1 and the reload register should be set to 255. This will cause counting to be as
slow as possible and consume minimum power.
As for general-purpose timers, Timer A has seven separate subtimer units, A1 and A2–A7,
that are also referred to as timers.
that are also referred to as timers.
Most likely, if a serial port is going to be used and a timer is needed to provide the baud clock,
that timer will be set up to be driven directly from the clock, and the interrupt associated with
that timer will be disabled. (Serial port interrupts are generated by the serial port logic.)
that timer will be set up to be driven directly from the clock, and the interrupt associated with
that timer will be disabled. (Serial port interrupts are generated by the serial port logic.)
The value in the reload register can be changed while the timer is running to change the period
of the next timer cycle. When the reload register is initialized, the contents of the count-
down counter may be unknown, for example, during power-up initialization. If interrupts
are enabled, then the first interrupt may take place at an unknown time. Similarly, if the timer
output is being used to drive the clock for a parallel port or serial port, the first clock may
come at a random time. If a periodic clock is desired, it is probably not important when the
first clock takes place unless a phase relationship is desired relative to a different timers.
of the next timer cycle. When the reload register is initialized, the contents of the count-
down counter may be unknown, for example, during power-up initialization. If interrupts
are enabled, then the first interrupt may take place at an unknown time. Similarly, if the timer
output is being used to drive the clock for a parallel port or serial port, the first clock may
come at a random time. If a periodic clock is desired, it is probably not important when the
first clock takes place unless a phase relationship is desired relative to a different timers.
A phase relationship between two timers can be obtained in several ways. One way is to
set both reload registers to zero and to wait long enough for both timers to reload (maxi-
mum 256 clocks). Then both timers’ reload registers can be set to new values before or
after both are clocked.
set both reload registers to zero and to wait long enough for both timers to reload (maxi-
mum 256 clocks). Then both timers’ reload registers can be set to new values before or
after both are clocked.