Jameco Electronics 3000 ユーザーズマニュアル

When the clock doubler is used and there is no subsequent division of the clock, the output 
clock will be asymmetric, as shown in Figure 7-2.

The doubled-clock low time is subject to wide (50%) variation since it depends on process 
parameters, temperature, and voltage. The times given above are for a supply voltage of 
3.3 V and a temperature of 25°C. The doubled-clock low time increases by 20% when the 
voltage is reduced to 2.5 V, and increases by about 40% when the voltage is reduced fur-
ther to 2.0 V. The values increase or decrease by 1% for each 5°C increase or decrease in 
temperature. The doubled clock is created by xor’ing the delayed and inverted clock with 
itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will 
have a slightly different length. Since the duty cycle of the built-in oscillator can be as 
asymmetric as 52-48, the clock generated by the clock doubler will exhibit up to a 4%