Jameco Electronics 3000 ユーザーズマニュアル
User’s Manual
85
variation in period on alternate clocks. This does not affect the no-wait states memory
access time since two adjacent clocks are always used. However, the maximum allowed
clock speed must be slightly reduced if the clock is supplied via the clock doubler. The
only signals clocked on the falling edge of the clock are the memory and I/O write pulses
and the early option memory output enable. See Chapter 8 for more information on the
early output enable and write enable options.
access time since two adjacent clocks are always used. However, the maximum allowed
clock speed must be slightly reduced if the clock is supplied via the clock doubler. The
only signals clocked on the falling edge of the clock are the memory and I/O write pulses
and the early option memory output enable. See Chapter 8 for more information on the
early output enable and write enable options.
The spectrum spreader either stretches or shrinks the low plateau of the clock by a maxi-
mum of 3 ns for the normal spreading and 4.5 ns for the strong spreading. If the clock dou-
bler is used this will cause an additional asymmetry between alternate clock cycles.
mum of 3 ns for the normal spreading and 4.5 ns for the strong spreading. If the clock dou-
bler is used this will cause an additional asymmetry between alternate clock cycles.
The power consumption is proportional to the clock frequency, and for this reason power
can be reduced by slowing the clock when less computing activity is taking place. The
clock doubler provides a convenient method of temporarily speeding up or slowing down
the clock as part of a power management scheme.
can be reduced by slowing the clock when less computing activity is taking place. The
clock doubler provides a convenient method of temporarily speeding up or slowing down
the clock as part of a power management scheme.