Motorola MCF5281 ユーザーズマニュアル

MOTOROLA

Chapter 6.  ColdFire Flash Module (CFM)  

6-19

For proper program and erase operations, it is critical to set
f

CLK

 between 150 kHz and 200 kHz. Array damage due to

overstress can occur when f

CLK

 is less than 150 kHz.

Incomplete programming and erasure can occur when f

CLK

 is

greater than 200 kHz.

Command execution time increases proportionally with the
period of f

CLK

.

When CFMCLKD is written, the DIVLD bit is set automatically. If DIVLD is 0,
CFMCLKD has not been written since the last reset. Program and erase commands will not
execute if this register has not been written (see Section 6.4.3.4, “Flash User Mode Illegal
Operations”). 

A command state machine is used to supervise the write sequencing of program, erase, and
verify commands. To prepare for a command, the CFMUSTAT[CBEIF] flag should be
tested to ensure that the address, data, and command buffers are empty. If CBEIF is set, the
command write sequence can be started. 

This three-step command write sequence must be strictly followed. No intermediate writes
to the CFM module are permitted between these three steps. The command write sequence
is:

1. Write the 32-bit longword to be programmed to its location in the CFM array. The 

address and data will be stored in internal buffers. All address bits are valid for 
program commands. The value of the data written for verify and erase commands is 
ignored. For mass erase or verify, the address can be any location in the CFM array. 
For page erase, address bits [9:0] are ignored.

The page erase command operates simultaneously on adjacent
erase pages in two interleaved Flash physical blocks. Thus, a
single erase page is effectively 2 Kbyte. 

2. Write the program, erase, or verify command to CFMCMD, the command buffer. 

3. Launch the command by writing a 1 to the CBEIF flag. This clears CBEIF. When 

command execution is complete, the Flash state machine sets the CCIF flag. The 
CBEIF flag is also set again, indicating that the address, data, and command buffers 
are ready for a new command sequence to begin.