Motorola MCF5281 ユーザーズマニュアル

6-20

MOTOROLA

 

The Flash state machine flags errors in command write sequences by means of the
ACCERR and PVIOL flags in the CFMUSTAT register. An erroneous command write
sequence self-aborts and sets the appropriate flag. The ACCERR or PVIOL flags must be
cleared before commencing another command write sequence.

By writing a 0 to CBEIF, a command sequence can be aborted
after the longword write to the CFM array or the command
write to the CFMCMD and before the command is launched.
The ACCERR flag will be set on aborted commands and must
be cleared before a new command write sequence.

A summary of the programming algorithm is shown in Figure 6-13. The flow is similar for
the erase and verify algorithms with the exceptions noted in step 1 above.

Table 6-13 summarizes the valid Flash user commands.

 

0x05

Erase

verify

Verify that all 256 Kbytes of Flash from two interleaving physical 
blocks are erased. If both blocks are erased, the BLANK bit will be set 
in the CFMUSTAT register upon command completion.

0x20

 Program

Program a 32-bit longword.

0x40

Page

erase

Erase 2 Kbyte of Flash. Two 1024-byte pages from interleaving 
physical blocks are erased in this operation.

0x41

Mass

erase

Erase all 256 Kbytes of Flash from two interleaving physical blocks. A 
mass erase is only possible when no PROTECT bits are set for that 
block. 

0x06

Page erase

verify

Verify that the two 1024-byte pages are erased. If both pages are erased, 
the BLANK bit will be set in the CFMUSTAT register upon command 
completion.