Motorola MCF5281 ユーザーズマニュアル
11-2
MCF5282 User’s Manual
MOTOROLA
Interrupt/General-Purpose I/O Pin Descriptions
NOTE
The low-power interrupt control register (LPICR) in the
System Control Module specifies the interrupt level at or above
which is needed to bring the device out of a low-power mode.
System Control Module specifies the interrupt level at or above
which is needed to bring the device out of a low-power mode.
Table 11-1. Edge Port Module Operation in Low-power Modes
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It
may be configured to exit the low-power modes by generating an interrupt request on either
a selected edge or a low level on an external pin. In stop mode, there are no clocks available
to perform the edge-detect function. Only the level-detect logic is active (if configured) to
allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit
stop mode.
may be configured to exit the low-power modes by generating an interrupt request on either
a selected edge or a low level on an external pin. In stop mode, there are no clocks available
to perform the edge-detect function. Only the level-detect logic is active (if configured) to
allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit
stop mode.
NOTE
The input pin synchronizer is bypassed for the level-detect
logic since no clocks are available.
logic since no clocks are available.
11.3 Interrupt/General-Purpose I/O Pin Descriptions
All pins default to general-purpose input pins at reset. The pin value is synchronized to the
rising edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values
used in the edge/level detect logic are also synchronized to the rising edge of CLKOUT.
These pins use Schmitt triggered input buffers which have built in hysteresis designed to
decrease the probability of generating false edge-triggered interrupts for slow rising and
falling input signals.
rising edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values
used in the edge/level detect logic are also synchronized to the rising edge of CLKOUT.
These pins use Schmitt triggered input buffers which have built in hysteresis designed to
decrease the probability of generating false edge-triggered interrupts for slow rising and
falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by
the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at
reset.
the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at
reset.
Low-power Mode
EPORT Operation
Mode Exit
Wait
Normal
Any IRQx Interrupt at or above level in LPICR
Doze
Normal
Any IRQx Interrupt at or above level in LPICR
Stop
Level-sensing Only
Any IRQx Interrupt set for level-sensing at or above
level in LPICR