Motorola MCF5281 ユーザーズマニュアル
11-4
MCF5282 User’s Manual
MOTOROLA
Memory Map and Registers
11.4.2.1 EPORT Pin Assignment Register (EPPAR)
11.4.2.2 EPORT Data Direction Register (EPDDR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
EPPA7
EPPA6
EPPA5
EPPA4
EPPA3
EPPA2
EPPA1
—
Reset
0000_0000_0000_0000
R/W
R/W
R
Address
IPSBAR + 0x0013_0000, 0x0013_0001
Figure 11-2. EPORT Pin Assignment Register (EPPAR)
Table 11-3. EPPAR Field Descriptions
Bit(s)
Name
Description
15–2
EPPAx
EPORT pin assignment select fields. The read/write EPPAx fields configure EPORT pins for
level detection and rising and/or falling edge detection.
Pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a
valid interrupt request. Level-sensitive interrupt inputs are not latched. To guarantee that a
level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal
asserted until acknowledged by software. Level sensitivity must be selected to bring the device
out of stop mode with an IRQx interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt
generation. A pin configured for edge detection can trigger an interrupt regardless of its
configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt controller
module. EPPAR functionality is independent of the selected pin direction.
Reset clears the EPPAx fields.
00 Pin IRQx level-sensitive
01 Pin IRQx rising edge triggered
10 Pin IRQx falling edge triggered
11 Pin IRQx both falling edge and rising edge triggered
level detection and rising and/or falling edge detection.
Pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a
valid interrupt request. Level-sensitive interrupt inputs are not latched. To guarantee that a
level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal
asserted until acknowledged by software. Level sensitivity must be selected to bring the device
out of stop mode with an IRQx interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt
generation. A pin configured for edge detection can trigger an interrupt regardless of its
configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt controller
module. EPPAR functionality is independent of the selected pin direction.
Reset clears the EPPAx fields.
00 Pin IRQx level-sensitive
01 Pin IRQx rising edge triggered
10 Pin IRQx falling edge triggered
11 Pin IRQx both falling edge and rising edge triggered
1–0
—
Reserved, should be cleared.
7
6
5
4
3
2
1
0
Field
EPDD7
EPDD6
EPDD5
EPDD4
EPDD3 EPDD2 EPDD1
—
Reset
0000_0000
R/W
R/W
R
Address
IPSBAR + 0x0013_0002
Figure 11-3. EPORT Data Direction Register (EPDDR)