Motorola MC9S12GC-Family ユーザーズマニュアル
Device User Guide — 9S12C128DGV1/D V01.05
109
B.6 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
Phase-Locked-Loop (PLL).
B.6.1 Startup
Table B-10 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
B.6.1.1 POR
The release level V
PORR
and the assert level V
PORA
are derived from the V
DD
Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
B.6.1.2 LVR
The release level V
LVRR
and the assert level V
LVRA
are derived from the V
DD
Supply. They are also valid
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
B.6.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
Table B-10 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1
T
POR release level
V
PORR
2.07
V
2
T
POR assert level
V
PORA
0.97
V
3
D
Reset input pulse width, minimum input time
PW
RSTL
2
t
osc
4
D
Startup from Reset
n
RST
192
196
n
osc
5
D
Interrupt pulse width, IRQ edge-sensitive
mode
mode
PW
IRQ
20
ns
6
D
Wait recovery startup time
t
WRS
14
t
cyc