Motorola MC9S12GC-Family ユーザーズマニュアル
Device User Guide — 9S12C128DGV1/D V01.05
123
C.3 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in
with the actual timing
values shown on table Table C-4. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
C.3.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
assume a balanced load across all outputs.
Figure C-5 General External Bus Timing
Addr/Data
(read)
(read)
Addr/Data
(write)
(write)
addr
data
data
5
10
11
8
16
6
ECLK
1, 2
3
4
addr
data
data
12
15
9
7
14
13
LSTRB
22
NOACC
25
PIPO0
PIPO1, PE6,5
PIPO1, PE6,5
28
20
21
23
26
29
24
27
R/W
17
19
18
PE4
PA, PB
PA, PB
PE2
PE3
PE7