Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 15
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30
X19A-A-002-18
.
Figure 3-2: Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
Figure 3-3: Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
Power
Management
S1D13504
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CL
K
I
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
MC68000
BUS
BUS
RESET#
LDS#
D[15:0]
AS#
R/W#
DTACK#
A[20:1]
BCLK
AB0#
RD/WR#
AB[20:1]
DB[15:0]
WE1#
BS#
M/R#
CS#
BUSCLK
S
U
SPE
N
D
#
WAIT#
RESET#
A[23:21]
FC0, FC1
Decoder
Decoder
UDS#
LCDPWR
WE
#
A
[11:
0]
D[
15
:0
]
R
AS#
1Mx16
LCA
S
#
U
C
AS#
M
A
[11:
0]
M
D
[15:
0]
WE
#
R
AS#
LCA
S
#
U
C
AS#
FPM/EDO-DRAM
Power
Management
S1D13504
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLK
I
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
MC68030
BUS
RESET#
SIZ0
D[31:16]
AS#
R/W#
SIZ1
DSACK1#
A[20:0]
BCLK
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
S
U
SPEN
D
#
WAIT#
RESET#
A[31:21]
FC0, FC1
Decoder
Decoder
DS#
LCDPWR
WE
#
A
[8:
0]
D[
1
5
:0
]
RA
S
#
256Kx16
LCA
S
#
U
C
AS#
MA[
8
:0
]
M
D
[15:
0]
WE
#
RA
S
#
LCA
S
#
U
C
AS#
FPM/EDO-DRAM