Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
7-66
Freescale Semiconductor
Real-Time Clock
Periodic interrupts are separately enabled by control bits, and a global enable must be asserted to allow any of the periodic sources to generate
a CPU interrupt. Clearing Periodic interrupts is accomplished by writing 1 to the appropriate status bit.
a CPU interrupt. Clearing Periodic interrupts is accomplished by writing 1 to the appropriate status bit.
Stopwatch and Alarm interrupts are enabled simply by initiating the function. In the Stopwatch case, this means starting the Stopwatch, in the
Alarm case, this means enabling the Alarm. Clearing Stopwatch or Alarm interrupts is accomplished by writing 1 to the appropriate status bit.
Alarm case, this means enabling the Alarm. Clearing Stopwatch or Alarm interrupts is accomplished by writing 1 to the appropriate status bit.
Either of the RTC interrupts to the CPU can be used to awaken the MPC5200B from any power down mode.
7.6.1
Real-Time Clock Signals
®
MC-405 32.768KHz quartz crystal oscillator.
NOTE
External component values are highly dependent on the crystal. These values will be different for
different brands of crystals.
different brands of crystals.
Figure 7-4. Diagram—Suggested Crystal Oscillator Circuit
7.6.2
Programming Note
Accesses to the RTC control registers are performed on the IP bus clock domain, but the RTC itself runs on the (much) slower 32KHz crystal
domain. When software initiates a setting of the Time and/or Date, it must be realized that many IP bus clocks may go by before the setting
actually takes effect. If this is a system concern then it is recommended that software poll the Time and/or Date Status fields to confirm the
setting has occurred. This requires some careful bit manipulation of the expected status versus the written control values, particularly if the
output status is designated as 12-Hour format (input control format is always 24-Hour).
domain. When software initiates a setting of the Time and/or Date, it must be realized that many IP bus clocks may go by before the setting
actually takes effect. If this is a system concern then it is recommended that software poll the Time and/or Date Status fields to confirm the
setting has occurred. This requires some careful bit manipulation of the expected status versus the written control values, particularly if the
output status is designated as 12-Hour format (input control format is always 24-Hour).
It should be noted that updates to the RTC control registers, such as time and date set, must be synchronized with the 32KHz clock domain.
It can take four 32KHz clock cycles for this synchronizing hand shake to complete. Multiple time/date updates made within this four clock
synchronizing period may not be properly accepted by the RTC logic.
It can take four 32KHz clock cycles for this synchronizing hand shake to complete. Multiple time/date updates made within this four clock
synchronizing period may not be properly accepted by the RTC logic.
7.6.3
RTC Interface Registers—MBAR + 0x0800
RTC uses 8 32-bit registers. These registers are located at an offset from MBAR of 0x0800. Register addresses are relative to this offset.
Therefore, the actual register address is:
Therefore, the actual register address is:
MBAR + 0x0800 + register address
Hyperlinks to the Interrupt Controller registers are provided below:
Table 7-55. Real-Time Clock Signals
Signal
I/O
Definition
RTC_XTAL_IN
I
Real-time Clock External Crystal/External Clock Input
RTC_XTAL_OUT
O
Real-time Clock External Crystal
•
(0x0800)
•
RTC Current Date Register (0x0814)
, read-only
•
(0x0804)
•
,
read-only
RTC_XTAL_IN
R1
RTC_XTAL_OUT
R2
C2
C1
MC-405
12pF
500K
Ω
20M
Ω
12pF