Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

9-3

The block diagram of the LocalPlus Controller (LPC) is shown in 

This diagram shows the non-multiplexed implementation of 

address and data lines. 

The LPC is driven by the internal IP bus clock and the PCI_CLOCK. The supported ratios of the IP bus clock to the reference clock 
PCI_CLOCK (the one externally seen by peripherals) are 4:1, 2:1 and 1:1.

The reference clock is the PCI_CLOCK and all clock counts are referred to this clock. All transitions are synchronized to the rising edge of 
the PCI_CLOCK.

Start/Stop registers to define the CS address range for each CS output are contained in the MPC5200B MMAP register group, see 

. Registers in the LPC are accessed through the address range specified in the MPC5200B 

Internal Register Map. For more information, see 

. These registers control the operation of a particular CS 

and peripheral, when a "hit" occurs in the MMAP module for the corresponding CS space.

BestComm Interface + FiFo not shown

Not all pins are used in all modes.

For multiplexed bus implementation, external logic is required to capture the address phase as shown in 

.

XL Bus

Registers

IP bus Data

8

cs “hit”

MMAP

32

ext_add

Shared Data

Variable Width

Address

Variable Width

R/W Data

R/W

ACK

CS[0:7]

AD[31:0]

AD bus Grant

AD bus Request

ALE

8

TS

OE

PCI_CLOCK

PCI Arbiter

CDM

IPB_CLK

multiplexed

with PCI, ATA

TSIZ[1:2]

2