Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-54
Freescale Semiconductor
Functional Description
10.4.4.2
Configuration Mechanism
In order to support both Type 0 and Type 1 configuration transactions, MPC5200B provides the 32 bit Configuration Address Register (CAR),
located at module address 0x1F8. The register specifies the target PCI bus, device, function, and configuration register to be accessed. A read
or a write to the MPC5200B window defined as PCI I/O space, in PCIIWCR, causes the host bridge to translate the access into a PCI
configuration cycle if the enable bit in the Configuration Address Register is set and the device number does not equal 0b1_1111. For space
to be defined as I/O space, the accessed space (one of the initiator Windows) must be programmed as I/O, not memory.
located at module address 0x1F8. The register specifies the target PCI bus, device, function, and configuration register to be accessed. A read
or a write to the MPC5200B window defined as PCI I/O space, in PCIIWCR, causes the host bridge to translate the access into a PCI
configuration cycle if the enable bit in the Configuration Address Register is set and the device number does not equal 0b1_1111. For space
to be defined as I/O space, the accessed space (one of the initiator Windows) must be programmed as I/O, not memory.
The format of the Configuration Address Register is shown in
. When MPC5200B detects an access to an I/O Window, it checks the enable flag and the device number in the
Configuration Address Register. If the enable bit is set, and the device number is not 0b1_1111, the MPC5200B performs a configuration cycle
translation function and runs a configuration read or configuration write transaction on the PCI bus. The device number 0b1_1111 is used for
performing interrupt acknowledge and Special Cycle transactions. See
translation function and runs a configuration read or configuration write transaction on the PCI bus. The device number 0b1_1111 is used for
performing interrupt acknowledge and Special Cycle transactions. See
and
for more information. If the bus number corresponds to the local PCI bus (bus number = 0x00), a Type
0 configuration cycle transaction is performed. If the bus number indicates a remote PCI bus, MPC5200B performs a Type 1 configuration
cycle translation. If the enable bit is not set, the access to the Configuration Window is passed through to the PCI bus as a I/O space transaction
at the internal address (window translation applies).
cycle translation. If the enable bit is not set, the access to the Configuration Window is passed through to the PCI bus as a I/O space transaction
at the internal address (window translation applies).
Note that the PCI data byte enables (C/BE[3:0]) are determined by the size access to the Window.
10.4.4.2.1
Type 0 Configuration Translation
shows the Type 0 translation function performed on the contents of the Configuration Address Register to the AD[31:0] signals
on the PCI bus during the address phase of the configuration cycle (only applies when the Enable bit in the Configuration Address Register
is set).
is set).
011
101
--
--
--
OP3
OP4
OP5
OP6
OP7
000
0111
OP3
--
--
--
100
0000
OP7
OP6
OP5
OP4
000
110
OP2
OP3 OP4
OP5
OP6
OP7
--
--
000
0000
OP5
OP4
OP3
OP2
100
1100
--
--
OP7
OP6
001
110
--
OP2 OP3
OP4
OP5
OP6
OP7
--
000
0001
OP4
OP3
OP2
--
100
1000
--
OP7
OP6
OP5
010
110
--
--
OP2
OP3
OP4
OP5
OP6
OP7
000
0011
OP3
OP2
--
--
100
0000
OP7
OP6
OP5
OP4
000
111
OP1
OP2 OP3
OP4
OP5
OP6
OP7
--
000
0000
OP4
OP3
OP2
OP1
100
1000
--
OP7
OP6
OP5
001
111
--
OP1 OP2
OP3
OP4
OP5
OP6
OP7
000
0001
OP3
OP2
OP1
--
100
0000
OP7
OP6
OP5
OP4
000
000
OP0
OP1 OP2
OP3
OP4
OP5
OP6
OP7
000
0000
OP3
OP2
OP1
OP0
100
0000
OP7
OP6
OP5
OP4
a
The byte lane translation will be similar for other types of transactions. However, the PCI address may be different
as explained in
as explained in
Table 10-7. XLB bus to PCI Byte Lanes for Memory
a
Transactions (continued)
XL bus
PCI Bus
A
[29:31]
TSIZ
[0:2]
Data Bus Byte Lanes
AD
[2:0]
BE
[3:0]
31:2
4
23:1
6
15:8
7:0
0
1
2
3
4
5
6
7