Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-56
Freescale Semiconductor
Functional Description
NOTE: Device numbers 0b0_0000 to 0b0_1001 are reserved. Programming to these values and issuing a configuration transaction will
result in a PCI configuration cycle with AD31-AD11 driven low.
MPC5200B can issue PCI configuration transactions to itself. A Type 0 configuration initiated by MPC5200B can access its own
configuration space by asserting its IDSEL input signal. This is the only way MPC5200B can clear its own status register bits
(read-write-clear).
configuration space by asserting its IDSEL input signal. This is the only way MPC5200B can clear its own status register bits
(read-write-clear).
For Type 0 translations, the function number and dword fields are copied without modification onto the AD[10:2] signals and AD[1:0] are
driven low during the address phase.
driven low during the address phase.
10.4.4.2.2
Type 1 Configuration Translation
For Type 1 translations, the 30 high-order bits of the Configuration Address Register are copied without modification onto the AD[31:2]
signals during the address phase. The AD[1:0] signals are driven to 0b01 during the address phase to indicate a Type 1 configuration cycle.
signals during the address phase. The AD[1:0] signals are driven to 0b01 during the address phase to indicate a Type 1 configuration cycle.
10.4.4.2.3
Interrupt Acknowledge Transactions
When MPC5200B detects a read from an I/O-defined Window (
), it checks the enable flag, bus number, and the device number in the Configuration Address Register (
). If the enable bit is set, the bus number corresponds to the local PCI bus
(bus number = 0x00), and the device number is all 1’s (device number = 0b1_1111), then an interrupt acknowledge transaction is initiated. If
the bus number indicates a subordinate PCI bus (bus number != 0x00), a Type 1 configuration cycle is initiated, similar to any other
configuration cycle for which the bus number does not match. The function number and dword values are ignored.
the bus number indicates a subordinate PCI bus (bus number != 0x00), a Type 1 configuration cycle is initiated, similar to any other
configuration cycle for which the bus number does not match. The function number and dword values are ignored.
The interrupt acknowledge command (0b0000) is driven on the C/BE[3:0] signals and the address bus is driven with a stable pattern during
the address phase, but a valid address is not driven. The address of the target device during an interrupt acknowledge is implicit in the
command type. Only the system interrupt controller on the PCI bus should respond to the interrupt acknowledge and return the interrupt vector
on the data bus during the data phase. The size of the interrupt vector returned is indicated by the value driven on the C/BE[3:0] signals.
the address phase, but a valid address is not driven. The address of the target device during an interrupt acknowledge is implicit in the
command type. Only the system interrupt controller on the PCI bus should respond to the interrupt acknowledge and return the interrupt vector
on the data bus during the data phase. The size of the interrupt vector returned is indicated by the value driven on the C/BE[3:0] signals.
10.4.4.2.4
Special Cycle Transactions
When the MPC5200B detects a write to an I/O-defined Window (
), it checks the enable flag, bus number, and the device number in the Configuration Address Register (
). If the enable bit is set, the bus number corresponds to the local PCI bus
(bus number = 0x00), and the device number is all 1’s (device number = 0b1_1111), then a Special Cycle transaction is initiated. If the bus
number indicates a subordinate PCI bus (bus number != 0x00), a Type 1 configuration cycle is initiated, similar to any other configuration
cycle for which the bus number does not match. The function number and dword values are ignored.
number indicates a subordinate PCI bus (bus number != 0x00), a Type 1 configuration cycle is initiated, similar to any other configuration
cycle for which the bus number does not match. The function number and dword values are ignored.
The Special Cycle command (0b0001) is driven on the C/BE[3:0] signals and the address bus is driven with a stable pattern during the address
phase, but contains no valid address information. The Special Cycle command contains no explicit destination address, but broadcast to all
agents on the same bus segment. Each receiving agent must determine whether the message is applicable to it. PCI agent will never assert
DEVSEL in response to a Special Cycle command. Master Abort is the normal termination for a Special Cycle and no errors are reported for
this case of Master Abort termination. This command is basically a broadcast to all agents, and interested agents accept the command and
process the request.
phase, but contains no valid address information. The Special Cycle command contains no explicit destination address, but broadcast to all
agents on the same bus segment. Each receiving agent must determine whether the message is applicable to it. PCI agent will never assert
DEVSEL in response to a Special Cycle command. Master Abort is the normal termination for a Special Cycle and no errors are reported for
this case of Master Abort termination. This command is basically a broadcast to all agents, and interested agents accept the command and
process the request.
NOTE
Special Cycle commands do not cross PCI-to-PCI bridges. If a master wants to generate a Special
Cycle command on a specific bus in the hierarchy that is not its local bus, it must use a Type 1
configuration write command to do so. Type 1 configuration write commands can traverse
PCI-to-PCI bridges in both directions for the purpose of generating Special Cycle commands on any
bus in the hierarchy and are restricted to a single data phase in length. However, the master must know
the specific bus on which it desires to generate the Special Cycle command and cannot simply do a
broadcast to one bus and expect it to propagate to all buses.
Cycle command on a specific bus in the hierarchy that is not its local bus, it must use a Type 1
configuration write command to do so. Type 1 configuration write commands can traverse
PCI-to-PCI bridges in both directions for the purpose of generating Special Cycle commands on any
bus in the hierarchy and are restricted to a single data phase in length. However, the master must know
the specific bus on which it desires to generate the Special Cycle command and cannot simply do a
broadcast to one bus and expect it to propagate to all buses.
0b1_1101
29
AD29
0b1_1110
30
AD30
0b1_1111
31
-
Table 10-8. Type 0 Configuration Device Number to IDSEL Translation (continued)
Device Number
IDSEL
Binary
Decimal