Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

12-11

Each disable bit in the HC Interrupt Disable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The 
HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing a ‘1’ to a bit in this register clears the corresponding 
bit in the HcInterruptEnable register, whereas writing a ‘0’ to a bit in this register leaves the corresponding bit in the HcInterruptEnable register 
unchanged. On read, the current value of the HcInterruptEnable register is returned.

 

0

MIE

Master Interrupt Enable—used by HCD.

0 - writing to this bit is ignored by HC.

1 - writing to this bit enables interrupt generation, due to events specified in other bits of 
this register.

1

OC

OwnershipChange

0 - writing to this bit is ignored by HC.

1 - writing to this bit enables interrupt generation, due to ownership.

2:24

—

Reserved

25

RHSC

RootHubStatusChange

0 - Ignore

1 - Enable interrupt generation due to root hub status change.

26

FNO

FrameNumberOverflow

0 - Ignore

1- Enable interrupt generation due to frame number overflow.

27

UE

UnrecoverableError

0 - Ignore

1 - Enable interrupt generation due to unrecoverable error.

28

RD

ResumeDetected

0 - Ignore

1 - Enable interrupt generation due to resume detect.

29

SF

StartofFrame

0 - Ignore

1 - Enable interrupt generation due to start of frame.

30

WDH

WritebackDoneHead

0 - Ignore

1 - Enable interrupt generation due to HcDoneHead writeback.

31

SO

SchedulingOverrun

0 - Ignore

1 - Enable interrupt generation due to scheduling overrun.

msb  0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R

MIE

OC

Reserved

W

RESET:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0