Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
12-12
Freescale Semiconductor
Host Control (HC) Operational Registers
12.4.3
Memory Pointer Partition—MBAR + 0x1018
This HC partition uses 7 32-bit registers. These registers are located at an offset from MBAR of 0x1018. Register addresses are relative to
this offset. Therefore, the actual register address is:
this offset. Therefore, the actual register address is:
MBAR + 0x1018 + register address
The following registers are available:
•
(0x1018)
•
(0x101C)
•
(0x1020)
•
(0x1024)
•
(0x1028)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
RHSC
FNO
UE
RD
SF
WDH
SO
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0
MIE
Master Interrupt Enable—bit is set after a hardware or software reset.
0 written to this bit is ignored by HC.
1 written to this bit disables interrupt generation, due to events specified in other bits of this
register.
register.
1
OC
OwnershipChange
Ignore
Disable interrupt generation due to Ownership Change
2:24
—
Reserved
25
RHSC
RootHubStatusChange
Ignore
Disable interrupt generation due to root hub status change.
26
FNO
FrameNumberOverflow
Ignore
Disable interrupt generation due to frame number overflow.
27
UE
UnrecoverableError
Ignore
Disable interrupt generation due to unrecoverable error.
28
RD
ResumeDetected
Ignore
Disable interrupt generation due to resume detect.
29
SF
StartofFrame
Ignore
Disable interrupt generation due to start of frame.
30
WDH
WritebackDoneHead
Ignore
Disable interrupt generation due to HcDoneHead writeback.
31
SO
SchedulingOverrun
Ignore
Disable interrupt generation due to scheduling overrun.