Freescale Semiconductor MPC5200B ユーザーズマニュアル

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Host Control (HC) Operational Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
12-13
 (0x102C)
12.4.3.1
USB HC HCCA Register—MBAR + 0x1018
The HC HCCA register contains the physical address of the Host Controller Communication Area. HCD determines alignment restrictions 
by writing all 1s to HcHCCA and reading the HcHCCA content. Alignment is evaluated by examining the number of 0s in the lower order 
bits. Minimum alignment is 256Bytes. Bits 0 through 7 must always return 0 when read. This area holds control structures and the interrupt 
table, which are accessed by both the HC and HCD.
 
12.4.3.2
USB HC Period Current Endpoint Descriptor Register —MBAR + 0x101C
The HC Period Current Endpoint Descriptor (ED) register contains the physical address of the current isochronous or interrupt endpoint 
descriptor.
 
Table 12-7. USB HC HCCA Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
HCCA
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
HCCA
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:23
HCCA
Host Controller Communication Area—base address.
24:31
Reserved
Table 12-8. USB HC Period Current Endpoint Descriptor Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PCED
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
PCED
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:27
PCED
PeriodCurrentED—HC uses this field to point to the head of one of the Periodic lists, which is 
processed in the current Frame. HC updates register content after a periodic ED is processed. 
HCD may read the content in determining which ED is currently being processed at the time 
of reading.
28:31
Reserved