Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

15-51

The serial BitClk and the FrameSync can either be inputs that come from an external Codec device, or they can be internally generated by the 
PSC and provided as outputs to the external device, under control of bit 

[GenClk]. When the bit 

[GenClk] is set to zero then the 

BitClk and the FrameSync are inputs. In this case the FrameSync width can be anything from one BitClk period up to the total FrameSync 
length/period minus one BitClk. If the GenClk bit set to one, then the MPC5200 PSC generate the BitClk and the FrameSync signal. 

shows how the PSC generate the clocks.

TxD

Transmitter Serial Data Output—Data is shifted out on TxD on the falling or rising edge of the clock source. 
Transfers can be specified as either lsb or msb first. TxD is held low when Tx is disabled or idle.

- data shifted out on the rising edge of CLK if 

[ClkPol] = 0 

- data shifted out on the falling edge of CLK if 

[ClkPol] = 1 

and

- data send msb first if 

[SHDIR] = 0

- data send lsb first if 

[SHDIR] = 1

RxD

Receiver Serial Data Input—Data received on RxD is sampled on the falling or rising edge of the clock 
signal. Transfers can be specified as either lsb or msb first.

- data sampled on the rising edge of CLK if 

[ClkPol] = 1

- data sampled on the falling edge of CLK if 

[ClkPol] = 0

and

- data sampled msb first if 

[SHDIR] = 0

- data sampled lsb first if 

[SHDIR] = 1

Frame

Frame Sync—In Codec mode Frame can be driven from an external Codec or can be generate by the 
internal clock logic. Frame can be programmed as active High or active Low.

- the frame sync input from the external Codec if 

[GenClk] = 0

- the frame sync output to the external Codec if 

[GenClk] = 1

and

- frame sync is active low if 

[SyncPol] = 0

- frame sync is active high if 

[SyncPol] = 1

CLK

Bit Clock— In Codec mode CLK is:

•     - the clock input from the external Codec if 

[GenClk] = 0

•     - the clock output to the external Codec if 

[GenClk] = 1

Mclk

Clock output for an external Codec

Mclk divider

BitClk divider

Frame divider

PSC

CDM

f

system

Mclk

BitClk

Frame

MclkDiv[8:0] + 1

CCR[8:23]

CCR[0:7]

CTUR[0:7]