Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
19-34
Freescale Semiconductor
Functional Description
19.7.6
Timer Link
The MSCAN generates an internal time stamp whenever a valid frame is received or transmitted and the TIME bit is enabled. Because the
CAN specification defines a frame to be valid if no errors occur before the End of Frame (EOF) field is transmitted successfully, the actual
value of an internal timer is written at EOF to the appropriate time stamp position within the transmit buffer. For receive frames the time stamp
is written to the receive buffer.
CAN specification defines a frame to be valid if no errors occur before the End of Frame (EOF) field is transmitted successfully, the actual
value of an internal timer is written at EOF to the appropriate time stamp position within the transmit buffer. For receive frames the time stamp
is written to the receive buffer.
19.7.7
Modes of Operation
19.7.7.1
Normal Modes
The MSCAN module behaves as described within this specification in all normal modes.
19.7.7.2
Listen-Only Mode
In an optional bus monitoring mode (Listen-Only), the CAN node is able to receive valid data frames and valid remote frames, but it sends
only “recessive” bits on the CAN bus. In addition it cannot start a transmission. If the MAC sub-layer is required to send a “dominant” bit
(ACK bit, overload flag, active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant bit, although the
CAN bus may remain in recessive state externally.
only “recessive” bits on the CAN bus. In addition it cannot start a transmission. If the MAC sub-layer is required to send a “dominant” bit
(ACK bit, overload flag, active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant bit, although the
CAN bus may remain in recessive state externally.
19.7.8
Low Power Options
If the MSCAN is disabled (CANE=0), the MSCAN clocks are stopped for power savings.
If the MSCAN is enabled (CANE=1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode:
Sleep and Power Down Mode. In Sleep Mode power consumption is reduced by stopping all clocks except those to access the registers from
the CPU side. In Power Down Mode, all clocks are stopped and no power is consumed.
Sleep and Power Down Mode. In Sleep Mode power consumption is reduced by stopping all clocks except those to access the registers from
the CPU side. In Power Down Mode, all clocks are stopped and no power is consumed.
summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings
on the CSWAI and SLPRQ/SLPAK bits.
For all modes, an MSCAN Wake-Up interrupt can only occur if the MSCAN is in Sleep Mode (SLPRQ=1 and SLPAK=1), wake-up
functionality is enabled (WUPE=1) and the Wake-Up interrupt is enabled (WUPIE=1).
functionality is enabled (WUPE=1) and the Wake-Up interrupt is enabled (WUPIE=1).
5 .. 12
4 .. 11
4
3
1 .. 4
0 .. 3
6 .. 13
5 .. 12
5
4
1 .. 4
0 .. 3
7 .. 14
6 .. 13
6
5
1 .. 4
0 .. 3
8 .. 15
7 .. 14
7
6
1 .. 4
0 .. 3
9 .. 16
8 .. 15
8
7
1 .. 4
0 .. 3
Table 19-35. CPU vs. MSCAN Operating Modes
Power Mode
MSCAN Mode
Normal
Power Down
Sleep
(CANE=0)
Full Power
CSWAI = X
a
SLPRQ = 0
SLPAK = 0
CSWAI = X
SLPRQ = 1
SLPRQ = 1
SLPAK = 1
CSWAI = X
SLPRQ = X
SLPAK = X
Sleep
CSWAI = 0
SLPRQ = 0
SLPAK = 0
CSWAI = 1
SLPRQ = X
SLPAK = X
CSWAI = 0
SLPRQ = 1
SLPAK = 1
CSWAI = X
SLPRQ = X
SLPAK = X
Deep Sleep
CSWAI = X
SLPRQ = X
SLPAK = X
CSWAI = X
SLPRQ = 1
SLPRQ = 1
SLPAK = 1
CSWAI = X
SLPRQ = X
SLPAK = X
Table 19-34. CAN Standard Compliant Bit Time Segment Settings (continued)
Time Segment 1
TSEG1
Time Segment 2
TSEG2
Synchronization
Jump Width
SJW