Freescale Semiconductor MPC5200B ユーザーズマニュアル

19-32

Freescale Semiconductor

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All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to 
be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers 

 serve as a lock to protect the following registers:

— MSCAN Control 1 Register (CANCTL1)
— MSCAN Bus Timing Registers 0 and 1 (CANBTR0, CANBTR1)
— MSCAN Identifier Acceptance Control Register (CANIDAC)
— MSCAN Identifier Acceptance Registers (CANIDAR0-7)
— MSCAN Identifier Mask Registers (CANIDMR0-7)

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The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the Power Down Mode or Initialization 
Mode (see 

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The MSCAN enable bit (CANE) is only writable once in normal modes as further protection against inadvertently disabling the 
MSCAN.

 shows the structure of the MSCAN clock generation circuitry. With this flexible clocking scheme, the MSCAN is able to handle 

CAN bus rates ranging from 10 Kbps up to 1 Mbps.

The clock source bit (CLKSRC) in the CANCTL1 register 

 

defines whether the internal CANCLK is connected to the output of the system oscillator clock (SYS_XTAL_IN) or to the IP bus clock.

Both MSCAN modules can have different selected clock sources. To select the oscillator clock the 
CLKSRC bit in the CANCTL1 register must be set.

The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, 
for high CAN bus rates (1 Mbps), a 45%-55% duty cycle of the clock is required.

Because the Bus Clock is generated from a PLL, it is recommended to select the Oscillator Clock rather than the Bus Clock due to jitter 
considerations, especially at the faster CAN bus rates.

A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the 
MSCAN.

A bit time is subdivided into three segments

1

 

2

 (reference 

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SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. 

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Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by 
setting the parameter TSEG1 to consist of 4 to 16 time quanta. 

1. For further explanation of the under-lying concepts please refer to ISO/DIS 11519-1, Section 10.3.
2. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing.

IP bus clock

Oscillator Clock

CANCLK

Time quanta clock (Tq)

f

Tq

f

CANCLK

Prescaler

value

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