Intel SR1640TH SR1640THNA ユーザーズマニュアル
製品コード
SR1640THNA
Intel® Server System SR1640TH TPS
Functional Architecture
Revision 1.0
Intel order number: E94847-001
11
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0xEB - Memory Test Error: If a DDR3 DIMM or a set of DDR3 DIMMs on the same
memory channel (row) fails HW Memory BIST but usable memory remains available,
the BIOS emits a beep code and displays POST Diagnostic LED code 0xEB
momentarily during the beeping and then continues POST. If all of the memory fails
HW Memory BIST, the system acts as if no memory is available, beeping and halting
with the POST Diagnostic LED code 0xE8 (No Usable Memory) displayed.
memory channel (row) fails HW Memory BIST but usable memory remains available,
the BIOS emits a beep code and displays POST Diagnostic LED code 0xEB
momentarily during the beeping and then continues POST. If all of the memory fails
HW Memory BIST, the system acts as if no memory is available, beeping and halting
with the POST Diagnostic LED code 0xE8 (No Usable Memory) displayed.
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0xEA - Channel Training Error: If the memory initialization process is unable to
properly perform the DQ/DQS training on a memory channel, the BIOS emits a beep
code and displays POST Diagnostic LED code 0xEA momentarily during the
beeping. If there is usable memory in the system on other channels, POST memory
initialization continues. Otherwise, the system halts with POST Diagnostic LED code
0xEA staying displayed.
properly perform the DQ/DQS training on a memory channel, the BIOS emits a beep
code and displays POST Diagnostic LED code 0xEA momentarily during the
beeping. If there is usable memory in the system on other channels, POST memory
initialization continues. Otherwise, the system halts with POST Diagnostic LED code
0xEA staying displayed.
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0xED - Population Error: If the installed memory contains a mix of RDIMMs and
UDIMMs, the system halts with POST Diagnostic LED code 0xED.
UDIMMs, the system halts with POST Diagnostic LED code 0xED.
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0xEE - Mismatch Error: If more than two quad-ranked DIMMs are installed on any
channel in the system, the system halts with POST Diagnostic LED code 0xEE.
channel in the system, the system halts with POST Diagnostic LED code 0xEE.
2.4.3.3
Publishing System Memory
The BIOS displays the Total Memory of the system during POST if Quiet Boot is
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the
system.
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the
system.
The BIOS displays the Effective Memory of the system in the BIOS Setup. The term
Effective Memory refers to the total size of all active DDR3 DIMMs (not disabled) and
not used as redundant units.
not used as redundant units.
The BIOS provides the total memory of the system in the main page of the BIOS
setup. This total is the same as the amount described by the first bullet in this
section.
section.
If Quiet Boot is disabled, the BIOS displays the total system memory on the
diagnostic screen at the end of POST. This total is the same as the amount
described by the first bullet in this section.
described by the first bullet in this section.
The BIOS provides the total amount of memory in the system.
2.4.3.3.1
Memory Reservation for Memory-mapped Functions
A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset,
processor, and BIOS (flash) spaces as memory-mapped I/O regions. This region appears as
a loss of memory to the operating system. In addition to this loss, the BIOS creates another
reserved region for memory-mapped PCIe functions, including a standard 64 MB or 256 MB
of standard PCI Express* MMIO configuration space.
processor, and BIOS (flash) spaces as memory-mapped I/O regions. This region appears as
a loss of memory to the operating system. In addition to this loss, the BIOS creates another
reserved region for memory-mapped PCIe functions, including a standard 64 MB or 256 MB
of standard PCI Express* MMIO configuration space.
If PAE is turned on in the operating system, the operating system reclaims all these reserved
regions.
regions.
In addition to this memory reservation, the BIOS creates another reserved region for
memory-mapped PCI Express* functions, including a standard 64 MB or 256 MB of standard
PCI Express* Memory Mapped I/O (MMIO) configuration space. This is based on the
selection of Maximize Memory below 4 GB in the BIOS Setup.
memory-mapped PCI Express* functions, including a standard 64 MB or 256 MB of standard
PCI Express* Memory Mapped I/O (MMIO) configuration space. This is based on the
selection of Maximize Memory below 4 GB in the BIOS Setup.
If this is set to Enabled, the BIOS maximizes usage of memory below 4 GB for an operating
system without PAE capability by limiting PCI Express* Extended Configuration Space to 64
buses rather than the standard 256 buses. This is done using the MAX_BUS_NUMBER
system without PAE capability by limiting PCI Express* Extended Configuration Space to 64
buses rather than the standard 256 buses. This is done using the MAX_BUS_NUMBER