Intel SR1640TH SR1640THNA ユーザーズマニュアル

Intel® Server System SR1640TH TPS 

Functional Architecture 

Revision 1.0 

 

 

 

Intel order number: E94847-001 

13 

5.  The DIMM identifiers on the silkscreen on the board provide information about the 

channel and the processor socket to which they belong. For example, DIMM_A1 
is the first slot on channel A. 

 

Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on 
the following factors: 

ƒ

 

Existing DDR3 DIMM population 

ƒ

 

DDR3 DIMM characteristics 

ƒ

 

Optimization techniques used by the Intel

®

 Xeon

®

 3400 processor to maximize 

memory bandwidth 

In the Independent Channel mode, all DDR3 channels operate independently. Slot-to-slot 
DIMM matching is not required across channels (for example, A1 and B1 do not have to 
match each other in terms of size, organization, and timing). DIMMs within a channel do not 
have to match in terms of size and organization, but they operate in the minimal common 
frequency. Also, Independent Channel mode can be used to support single DIMM 
configuration in channel A and in the Single Channel mode. 

You must observe the following general rules when selecting and configuring memory to 
obtain the best performance from the system. 

1.  DDR3 RDIMMs must always be populated using a fill-farthest method. 
2.  DDR3 UDIMMs must always be populated on DIMM A1/A2/B1/B2. 
3. Intel

® 

Xeon

®

 3400 Series Processors support either RDIMMs or UDIMMs. 

4.  RDIMM and UDIMM CANNOT be mixed. 
5.  The minimal memory set is {DIMMA1}. 
6.  DDR3 DIMMs on adjacent slots on the same channel do not need to be identical. 

Intel

®

 Server Systems SR1640TH that use the Intel

®

 3420 chipset support two slots per 

DDR3 channel, two DDR3 channels per processor socket. 
 

 

Channel A 

Channel B 

 

A1 

A2 

B1 

B2 

X      
X X    
X   X  
X X X  

RDIMM 

X X X X 
X      
X X    
X   X  
X X X  

UDIMM 

X X X X