Texas Instruments CC2650DK ユーザーズマニュアル
Introduction
14.1 Introduction
This section describes the functionality and design of the always-on, real-time clock (AON RTC) for the
CC26xx platform. The AON RTC implements a second and subsecond counter with support for software-
compensation of ppm-offsets, with three match and one compare register.
CC26xx platform. The AON RTC implements a second and subsecond counter with support for software-
compensation of ppm-offsets, with three match and one compare register.
A special mechanism is in place to support power down of the MCU domain while the AON RTC
continues to operate. The AON RTC is powered in all power modes except for the deepest power-down
mode, known as shutdown.
continues to operate. The AON RTC is powered in all power modes except for the deepest power-down
mode, known as shutdown.
14.2 Functional Specifications
This section gives a functional description of the AON RTC.
14.2.1 Functional Overview
The functionality of the AON RTC is described as follows:
•
Runs on always-on, 32-kHz clock
•
70-bit incrementing counter with support for programmable increment to support ppm-adjustment
•
Three general-purpose channels (0, 1, and 2) with comparators supporting the generation of events
•
Software and hardware reset of events
•
All events can be delayed by a programmable amount to generated corresponding delayed events.
•
A programmable set of the delayed events can be combined to generate a delayed combined event.
14.2.2 Free-Running Counter
The AON RTC implements a 70-bit, free-running counter incremented by a programmable value for each
32-kHz clock. The programmable value allows compensation of ppm-offsets in the 32-kHz clock, making it
possible for the counter to operate with a very high precision.
32-kHz clock. The programmable value allows compensation of ppm-offsets in the 32-kHz clock, making it
possible for the counter to operate with a very high precision.
The counter starts from 0 when enabled following power up of the AON RTC, but can also be reset to 0 or
any other new value by the software. The counter measures seconds
(32 bit) and subseconds (32 bit).
any other new value by the software. The counter measures seconds
(32 bit) and subseconds (32 bit).
By default, the AON RTC increments its counter with 1/32768 seconds each 32-kHz clock tick. A
subsecond increment value of 0x80 000 corresponds to 1/32768 seconds. Increasing or decreasing the
subsecond increments value increases or decreases the speed of the AON RTC by the same amount.
subsecond increment value of 0x80 000 corresponds to 1/32768 seconds. Increasing or decreasing the
subsecond increments value increases or decreases the speed of the AON RTC by the same amount.
Change the increment by updating the [AUX_WUC:RTCSUBSECINC0] and
[AUX_WUC:RTCSUBSECINC1] registers, and then load the new setting to the AON RTC by a write to the
[AUX_WUC:UPD_REQ] register. The new subsecond increment value must not be changed by AUX until
it has received an acknowledgment from the AON RTC. The acknowledgment can be read from
[AUX_WUC:UPD_ACK]. After the acknowledgment has been received, [AUX_WUC:UPD_REQ] can be
written back to 0 and a new subsecond increment can be uploaded, if needed.
[AUX_WUC:RTCSUBSECINC1] registers, and then load the new setting to the AON RTC by a write to the
[AUX_WUC:UPD_REQ] register. The new subsecond increment value must not be changed by AUX until
it has received an acknowledgment from the AON RTC. The acknowledgment can be read from
[AUX_WUC:UPD_ACK]. After the acknowledgment has been received, [AUX_WUC:UPD_REQ] can be
written back to 0 and a new subsecond increment can be uploaded, if needed.
14.2.3 Channels
The AON RTC contains three independent channels (0, 1, and 2) that have slightly different behaviors.
All channels can operate in a compare mode; each channel generates a compare event when a
programmable time limit has been reached or exceeded. This is the only mode of operation for channel 0.
programmable time limit has been reached or exceeded. This is the only mode of operation for channel 0.
Channel 1 can be operated in a capture mode, where an external event causes the current value of the
free-running timer to be latched, to remember the time of the event. A capture event is subsequently
generated. As the channel 1 timer is operating in either compare mode or capture mode, the same
physical event is generated in each mode.
free-running timer to be latched, to remember the time of the event. A capture event is subsequently
generated. As the channel 1 timer is operating in either compare mode or capture mode, the same
physical event is generated in each mode.
Channel 2 can operate in a continuous compare mode, automatically incrementing its compare value
following a compare event. This enables the generation of completely equidistant events.
following a compare event. This enables the generation of completely equidistant events.
shows the three AON RTC channels.
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SWCU117A – February 2015 – Revised March 2015
Real-Time Clock
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