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RTC Registers
The [AON_RTC:EVFLAGS] register has a fast-clear feature. When written to 1, the MCU intermediately
clears the EVFLAGS bit field. This process enables the MCU to clear the source quickly if the status is
used as an interrupt or event. Due to synchronization, the actual flag in the RTC is not cleared until 1 or 2
clock cycles later. For this reason, a new event will be masked for up to two 32-kHz LF periods.
clears the EVFLAGS bit field. This process enables the MCU to clear the source quickly if the status is
used as an interrupt or event. Due to synchronization, the actual flag in the RTC is not cleared until 1 or 2
clock cycles later. For this reason, a new event will be masked for up to two 32-kHz LF periods.
14.3.2 Entering and Wakeup From Sleep
Before entering sleep, the application must ensure that all write requests to the AON registers are
completed. The MCU domain register interface must be clocked to complete the synchronization towards
the AON domain. If the clock is stopped or halted before the synchronization has completed, the write
access might be lost.
completed. The MCU domain register interface must be clocked to complete the synchronization towards
the AON domain. If the clock is stopped or halted before the synchronization has completed, the write
access might be lost.
Upon wakeup from sleep, the application must wait for one 32-kHz LF period. This wait ensures that the
MCU domain register interface is correctly synchronized. If registers are read before synchronization is
completed, the value might not be updated. For example, reading the [AON_RTC:SEC] register might
show the value from before entering sleep, and not the current value.
MCU domain register interface is correctly synchronized. If registers are read before synchronization is
completed, the value might not be updated. For example, reading the [AON_RTC:SEC] register might
show the value from before entering sleep, and not the current value.
14.3.3 [AON_RTC:SYNC] Register
The [AON_RTC:SYNC] register synchronizes between the MCU domain and AON domain.
A read request from the [AON_RTC:SYNC] register will not return if there are outstanding write requests
to the AON registers; in other words, the bus is halted until all outstanding requests are completed.
to the AON registers; in other words, the bus is halted until all outstanding requests are completed.
A write request triggers a dummy write to the AON domain. This write can ensure synchronization to the
LF clock. This dummy write takes 1 to 2 32-kHz LF clock cycles.
LF clock. This dummy write takes 1 to 2 32-kHz LF clock cycles.
1. Write to [AON_RTC:SYNC] or any other register in the AON domain. The write will trigger an
outstanding write request to be registered on AON domain.
2. Read from [AON_RTC:SYNC]. This read will not return, until all outstanding requests are completed.
The [AON_RTC:SYNC] operation is typically used when a specific order must be ensured. For example,
when disabling a channel, [AON_RTC:SYNC] can be polled to ensure that the channel has been disabled
and no further events can occur:
when disabling a channel, [AON_RTC:SYNC] can be polled to ensure that the channel has been disabled
and no further events can occur:
1. Set [AON_RTC:CHCTL:CH2_EN] = 0
2. Read [AON_RTC:SYNC]
3. The channel is now disabled. No further events can occur.
Another typical use case for [AON_RTC:SYNC] is to ensure that all outstanding accesses are completed
prior to powering down the MCU power domain. A problem can occur if the MCU sets up a new wake-up
event (RTC timer), but powers down before the new RTC compare values are transferred to the AON
RTC.
prior to powering down the MCU power domain. A problem can occur if the MCU sets up a new wake-up
event (RTC timer), but powers down before the new RTC compare values are transferred to the AON
RTC.
1. Write a new compare value to [AON_RTC:CH1CMP:VALUE]
2. Read [AON_RTC:SYNC]
3. Put CM3 to sleep.
Another typical use is to ensure the correct values are updated in the MCU domain on wakeup. This MCU
domain is only updated on a positive edge of the 32-kHz LF clock.
domain is only updated on a positive edge of the 32-kHz LF clock.
1. Write to [AON_RTC:SYNC]
2. Read [AON_RTC:SYNC]
3. Other AON RTC registers can now be read safely, as their information is correctly updated.
14.4 Real-Time Clock Registers
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SWCU117A – February 2015 – Revised March 2015
Real-Time Clock
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