Texas Instruments CC2650DK ユーザーズマニュアル
I2S Registers
22.10.1.7 AIFWMASK2 Register (Offset = 18h) [reset = X]
AIFWMASK2 is shown in
and described in
.
Word Selection Bit Mask for Pin 2
Figure 22-14. AIFWMASK2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
MASK
R-X
R/W-3h
Table 22-8. AIFWMASK2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
7-0
MASK
R/W
3h
Bit-mask indicating valid channels in a frame on AD2 In single-phase
mode, each bit represents one channel, starting with LSB for the first
word in the frame. A frame can contain up to 8 channels. Channels
that are not included in the mask will not be sampled and stored in
memory, and clocked out as '0'. In dual-phase mode, only the two
LSBs are considered. For a stereo configuration, set both bits. For a
mono configuration, set bit 0 only. In mono mode, only channel 0 will
be sampled and stored to memory, and channel 0 will be repeated
when clocked out. In mono mode, only channel 0 will be sampled
and stored to memory, and channel 0 will be repeated in the second
phase when clocked out. If all bits are zero, no input words will be
stored to memory, and the output data lines will be constant '0'. This
can be utilized when PWM debug output is desired without any
actively used output pins.
mode, each bit represents one channel, starting with LSB for the first
word in the frame. A frame can contain up to 8 channels. Channels
that are not included in the mask will not be sampled and stored in
memory, and clocked out as '0'. In dual-phase mode, only the two
LSBs are considered. For a stereo configuration, set both bits. For a
mono configuration, set bit 0 only. In mono mode, only channel 0 will
be sampled and stored to memory, and channel 0 will be repeated
when clocked out. In mono mode, only channel 0 will be sampled
and stored to memory, and channel 0 will be repeated in the second
phase when clocked out. If all bits are zero, no input words will be
stored to memory, and the output data lines will be constant '0'. This
can be utilized when PWM debug output is desired without any
actively used output pins.
1430
Integrated Interchip Sound (I2S) Module
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated