Texas Instruments CC2650DK ユーザーズマニュアル
I2S Registers
22.10.1.9 AIFINPTRNEXT Register (Offset = 20h) [reset = X]
AIFINPTRNEXT is shown in
and described in
DMA Input Buffer Next Pointer
Figure 22-16. AIFINPTRNEXT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PTR
R/W-X
Table 22-10. AIFINPTRNEXT Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
PTR
R/W
X
Pointer to the first byte in the next DMA input buffer. The read value
equals the last written value until the currently used DMA input buffer
is completed, and then becomes null when the last written value is
transferred to the DMA controller to start on the next buffer. This
event is signalized by aif_dma_in_irq. At startup, the value should be
written once before and once after configuring the DMA buffer size in
AIFDMACFG. The next pointer must be written to this register while
the DMA function uses the previously written pointer. If not written in
time, IRQFLAGS.PTR_ERR will be raised and all input pins will be
disabled. Note the following limitations: - Address space wrapping is
not supported (i.e. address(last sample) must be higher than
address(first sample). - A DMA block cannot be aligned with the end
of the address space (i.e. a block cannot contain the address
0xFFFF)
equals the last written value until the currently used DMA input buffer
is completed, and then becomes null when the last written value is
transferred to the DMA controller to start on the next buffer. This
event is signalized by aif_dma_in_irq. At startup, the value should be
written once before and once after configuring the DMA buffer size in
AIFDMACFG. The next pointer must be written to this register while
the DMA function uses the previously written pointer. If not written in
time, IRQFLAGS.PTR_ERR will be raised and all input pins will be
disabled. Note the following limitations: - Address space wrapping is
not supported (i.e. address(last sample) must be higher than
address(first sample). - A DMA block cannot be aligned with the end
of the address space (i.e. a block cannot contain the address
0xFFFF)
1432
Integrated Interchip Sound (I2S) Module
SWCU117A – February 2015 – Revised March 2015
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