Texas Instruments CC2650DK ユーザーズマニュアル
Coretex-M3 Core Registers
2.5.2.2
Cortex General-Purpose Register 1 (R1)
Table 2-4. Cortex General-Purpose Register 1 (R1)
Address Offset
Reset
–
Physical Address
Instance
Description
The R1 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
2.5.2.3
Cortex General-Purpose Register 2 (R2)
Table 2-5. Cortex General-Purpose Register 2 (R2)
Address Offset
Reset
–
Physical Address
Instance
Description
The R2 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
2.5.2.4
Cortex General-Purpose Register 3 (R3)
Table 2-6. Cortex General-Purpose Register 3 (R3)
Address Offset
Reset
–
Physical Address
Instance
Description
The R3 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
35
SWCU117A – February 2015 – Revised March 2015
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