Texas Instruments CC2650DK ユーザーズマニュアル
Coretex-M3 Core Registers
2.5.2.5
Cortex General-Purpose Register 4 (R4)
Table 2-7. Cortex General-Purpose Register 4 (R4)
Address Offset
Reset
–
Physical Address
Instance
Description
The R4 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
2.5.2.6
Cortex General-Purpose Register 5 (R5)
Table 2-8. Cortex General-Purpose Register 5 (R5)
Address Offset
Reset
–
Physical Address
Instance
Description
The R5 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
2.5.2.7
Cortex General-Purpose Register 6 (R6)
Table 2-9. Cortex General-Purpose Register 6 (R6)
Address Offset
Reset
–
Physical Address
Instance
Description
The R6 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
36
SWCU117A – February 2015 – Revised March 2015
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